197th Meeting - Toronto, Ontario, Canada

May 14-18, 2000


I1 - Rapid Thermal and Other Short-Time Processing Technologies I

Electronics Division/ Dielectric Science and Technology Division/ High Temperature Materials Division

Monday, May 15, 2000

Cinema 2, Lower Concourse

Ultra-Shallow Junctions for Nanoscale CMOS I

Co-Chairs: K.S. Jones and J.C. Gelpey

10:00521 High Ramp Rate Rapid Thermal Annealing for Ultra-Shallow Junctions - S. Banerjee (University of Texas) PDF
10:30522 New Physics for Modeling Transient Enhanced Diffusion in RTP - E. Seebauer and M. Jung (University of Illinois) PDF
10:50523 Optical Effects in Diffusion and Activation Processes During RTA - R. Fair (Duke University) PDF
11:20524 Spike Annealing for Ultra-Shallow Junction Formation - A. Jain (Texas Instruments Inc.) PDF
11:40525 Inherent Radiative Differences between Rapid Thermal and Furnace Annealing: Their Effects on Dopant Diffusion and Activation - P. Choi and D.-L. Kwong (University of Texas at Austin) PDF

Ultra-Shallow Junctions for Nanoscale CMOS II

Co-Chairs: J.C. Gelpey and K.S. Jones

1:30526 Ultra-Shallow Junction Formation Using Conventional Ion Implantation and Rapid Thermal Annealing Technologies: Physical and Practical Limits - A. Agarwal (Eaton Corporation), H.-J. Gossmann, A.T. Fiory, V.C. Venezia, and D.C. Jacobson (Luce nt Technologies, Bell Laboratories) PDF
2:00527 Role of Silicon Interstitial and Boron Interstitial Clusters in Transient Enhanced Diffusion - N. Cowern (Philips Research Laboratories), G. Mannino (Universita di Catania), F. Roozeboom, P. Stolk, and J. Van Berkum (Philips Research Labora tories) PDF
2:30528 Characterization of Selectively Deposited Very-Heavily Boron-doped Silicon-Germanium Alloys for Ultra-Shallow Junctions and Advanced Contacts - S. Gannavaram and M. Ozturk (North Carolina State University) PDF
2:50529 Selective Epitaxial Si and SiGe for Elevated Source Drain MOSFETs - S.B. Samavedam, A. Dip, A.M. Phillips (Motorola), T. Mihopoulos (Motorola Computational Technologies Laboratory), J.M. Grant, W.J. Taylor, and P.J. Tobin (Motorola) PDF
3:20 Thirty-Minute Intermission

Contacts for Nanoscale CMOS

Co-Chairs: M. Ozturk and K. Reid

3:50530 Aspects of Co and Ti Salicide Processing - R. Tung and L. Kappius (Lucent Technologies Bell Labs) PDF
4:20531 Multi-Substrate CoSi2 Formation Kinetics in a Low-Pressure, Susceptor-Based RTP Tool - A. Atanos, V. Parihar (Mattson Technology, Inc.), and S.-P. Sun (Advanced Micro Devices) PDF
4:40532 Using Nitrogen (N2+) Implantation into Poly-Si/a-Si Film to Improve the Thermal Stability of Cobalt Silicide - K.-M. Chang, M.-H. Tseng, Y.-J. Haung, and I.-C. Deng (National Chiao Tung University) PDF
5:10533 Metal/Silicon Schottky Barrier Lowering by RTCVD Interface Passivation - Q.W. Ren, W. van Noort, L.K. Nanver, and J.W. Slotboom (Delft University of Technology) PDF

Tuesday, May 16, 2000

Ultra-Shallow Junctions for Nanoscale CMOS III

Co-Chairs: S. Banerjee and R.B. Fair

8:30534 Laser Thermal Processing (LTP) for Fabrication of Ultra-Shallow, Hyper-Abrupt, Highly Activated Junctions for Deca-Nanometer MOS Transistors - S. Talwar, Y. Wang, and C. Gelatos (Verdant Technologies) PDF
9:00535 Athermal Annealing of Neutron-Transmutation-Doped and Ion-Implanted Silicon - J. Grun, R.P. Fischer, M. Peckerar, C. Felix (Naval Research Laboratory), B.C. Covington (Southwest Texas State University), W.J. DeSisto (Naval Research Laborato ry), D.W. Donnelly (Sam Houston State University), C. Hoffman, J. Meyer, A. Ting, and C.K. Manka (Naval Research Laboratory) PDF
9:30536 Exploring Alternative Annealing Methods for Shallow Junction Formation in Ion Implanted Silicon - K.S. Jones, H. Banisaukis, C. Lindfors, M.E. Law, S. Earles (SWAMP Center), D. Downey (Varian Semiconductor Equipment Associates), and A. Agar wal (Eaton Corporation) PDF
10:00 Twenty-Minute Intermission
10:20537 Shallow Junction Challenges to Rapid Thermal Processing - L. Larson (SEMATECH) PDF

Panel Discussion

Co-Chairs: R.B. Fair and S. Banerjee

10:50 Panel Discussion

Gate Stacks for Nanoscale CMOS I

Co-Chairs: D.-L. Kwong and V. Misra

2:00538 Ultra Thin CVD Gate Dielectrics for 130 nm Technology Node - V. Watt, T.-Y. Luo, A. Karamcheti, H. Alshareef, M. Jackson, and H. Huff (Sematech) PDF
2:30539 High Performance, Highly Reliable Gate Oxide Formed with Rapid Thermal Oxidation In-Situ Steam Generation (ISSG) Technique - Y. Ma, Y. Chen, M. Brown, F. Li, Y. Chen (Bell Labs, Lucent Technologies), J. Eng, R. Opila, Y. Chabal, J. Sapjeta , D. Muller (Bell Labs, Lucent Technologies), G. Xing, T. Trowbridge, M. Khau, and N. Tam (Applied Materials) PDF
2:50540 High Reliable In Situ Steam Generation Process for 1.5-2.5nm Gate Oxides - M. Bidaud, F. Guyader (Centre Commun CNET STMicrolectronics), F. Glowacki (Applied Materials France), S. Bruyere, E. Vincent, and K. Barla (Centre Commun CNET STMicrolectronics) PDF
3:10541 Investigation of In-Situ Steam Generated Oxide (ISSG) followed by Remote Plasma Nitridation (RPN) for Effective Oxide Thickness Decrease and Gate Leakage Reduction - K. Eason (Stanford University), R. Jallepally, D. Noble (Applied Ma terials Inc.), S. Hattangady, R. Khamakar, and A. Rotondaro (Texas Instruments Inc.) PDF
3:30 Twenty-Minute Intermission
3:50542 Rapid Thermal Processing Using Steam - R. Sharangpani and S.-P. Tay (Steag RTP Systems) GIF
4:20543 Corona-Charge Evaluation of Thermal SiO2 Growth by Single Wafer and Batch Methods - J. Zhang, P. Frisella, J. Hebb, A. Agarwal (Eaton Semiconductor Equipment Operations), and A. Fiory (Bell Laboratories, Lucent Technologies, Inc. ) PDF
4:40544 Growth of Ultrathin Nitride on Si(100) by Rapid Thermal N2 Treatment - Z.-H. Lu (University of Toronto) and S.P. Tay (STEAG RTP Systems, Inc.) PDF
5:00545 Gate Dielectrics Formed by Remote Plasma Nitridation (RPN) of Ultrathin In-Situ Steam Generated (ISSG) Oxides - A. Karamcheti, T.-Y. Luo, H. Al-Shareef, V. Watt, M. Jackson, H. Huff (SEMATECH, Inc.), G. Xing, and R. Metevier (Applied Materials) PDF
5:20546 In-situ Rapid Thermal N2O Oxidation of NH3-Nitrided Si for Ultra Thin Nitride/Oxide Stack Gate Formation - Y.H. Kim, S.C. Song, H.F. Luan, A.L. Mao (The University of Texas at Austin), J. Gelpey (Steag RTP), and D.-L. Kwong (The University of Texas at Austin) PDF

Wednesday, May 17, 2000

New Applications of RTP

Co-Chairs: A. Fiory and D.-L. Kwong

10:00547 Mechanisms and Applications of the Control of Dopant Profiles in Silicon Using Si1-x-yGexCy Layers Grown by RTCVD - J. Sturm, M. Carroll, M. Yang, E. Stewart, and J. Gray (Princeton University) PDF
10:30548 High Performance Buried SiGe Channel PMOST Fabricated Using Rapid Thermal Processing and Shallow Trench Isolation - D. Tweet, S.T. Hsu, D. Evans, B. Ulrich, Y. Ono, and L. Stecker (Sharp Laboratories of America) PDF
10:50549 Kinetic Study of In-Situ Copper Oxidation and Reduction Using Rapid Thermal Procesing and Its Applications in ULSI - Y.Z. Hu, S.-P. Tay, and R. Sharangpani (Steag RTP Systems) GIF
11:10550 Development of RTA Process for the Crystallization of a-Si Thin Film - Y.-G. Yoon, T.-K. Kim, K.-B. Kim, J.-Y. Choi, B.-I. Lee, and S.-K. Joo (Seoul National Univ.) PDF

Gate Stacks for Nanoscale CMOS II

Co-Chairs: J.C. Gelpey and K. Reid

2:00551 Processing and Characterization of RTCVD Silicon Nitride and Oxynitride Grown in a Single Wafer RT Cluster Tool - C.P. D'Emic, E.P. Gusev, J. Newbury, P. Kozlowski, K.K. Chan, T. Zabel, and P. Varekamp (IBM - T. J. Watson Research Center) GIF
2:20552 Integrated Rapid Thermal CVD Oxynitride Gate Dielectric for Advanced CMOS Technology - H.-H. Tseng (Motorola) PDF
2:50553 Ultra Thin (EOT<7A) Ta2O5 Gate Stack Prepared by In-Situ RT-MOCVD Process - S.J. Lee, H.F. Luan, C.H. Lee (The University of Texas at Austin), R. Vrtis, D. Roberts (Schumacher), and D.L. Kwong (The University of Texas at Austin) PDF
3:10 Thirty-Minute Intermission
3:40554 High-k Oxides by Atomic Layer Chemical Vapour Deposition - M. Tuominen (ASM Microchemistry Ltd.) PDF
4:10555 Electrical and Chemical Properties of Ultra Thin RT-MOCVD Grown Ti-Doped Ta2O5 - S.J. Lee, H.F. Luan, A. Mao, T.S. Jeon, C.H. Lee (The University of Texas at Austin), R. Vrtis, D. Roberts (Schumacher), and D.L. Kwong ( The University of Texas at Austin) PDF
4:30556 Electrical and Material Properties of Metal Silicates Dielectrics and Metal Gates for Advanced CMOS Devices - V. Misra, M. Kulkarni, G. Heuss, H. Zhong, and H. Lazar (North Carolina State University) PDF
5:00557 RTCVD Polysilicon Grain Dimension Control - D. O'Meara, M. Rossow, H.-H. Tseng, J. Conner, V. Wang, T. Neil (Motorola), and C.-L. Chang (Applied Materials) PDF

Thursday, May 18, 2000

Advances in RTP Systems and Process Monitoring I

Co-Chairs: P. Timans and F. Roozeboom

9:00558 Optimization of Support Temperature in RTA-Tools by SIRD -Imaging of Monitor Wafers - H.D. Geiler, H. Karge (JenaWave Eng. & Consulting), and B. Krimbacher (Applied Materials GmbH) PDF
9:20559 Wafer Temperature Characterization During Low Temperature Annealing - W.S. Yoo and T. Fukada (WaferMasters, Inc.) PDF
9:40560 Determining the Uncertainty of Wafer Temperature Calibrations Resulting from Emissivity and Roughness Variations of Common Semiconductor Materials. - B. Adams (Applied Materials) PDF
10:10 Thirty-Minute Intermission
10:40561 Low Temperature Measurements and Monitors for Rapid Thermal Processing - P.J. Timans, N. Acharya, and I. Amarilio (STEAG RTP Systems) GIF
11:00562 In Situ Selectivity and Thickness Monitoring based on Quadrupole Mass Spectroscopy during Selective Silicon Epitaxy - E.A. Rying, G.L. Bilbro, M.C. Ozturk (North Carolina State University), and J.C. Lu (Georgia Institute of Technology) PDF
11:20563 Optimization and Control of Gas Flows in an RTCVD Reactor - Y. Rainova, K. Antonenko, A. Barchotkin (Moscow State Institute of Electronics Engineering), and J. Pezoldt (Institut fur Festkorperelektronik) PDF

Advances in RTP Systems and Process Monitoring II

Co-Chairs: B.A. Adams and M. Ozturk

1:30564 LEVITOR 4000: An Advanced RTP System Based on Conductive Heat Transfer - V.I. Kuznetsov, A.B. Storm, G.J. Snijders, C. De Ridder, E.H.A. Granneman (ASM International nv), T.A.M. Ruijl, and J.C.G. v.d. Sanden (Philips Center for Manufacturin g Technology) GIF
2:00565 Ultra-Shallow Junction Formation of BF2+ Implants Using a Low-Pressure, Hot-Wall Rapid Thermal Anneal - V. Parihar, A. Atanos, K. Reddy, and J.-F. Daviet (Mattson Technology, Inc.) PDF
2:20566 Temperature Gradient Rapid Thermal Processor - J.-M. Dilhac and C. Ganibal (LAAS-CNRS) PDF
2:40 Twenty-Minute Intermission
3:00567 Spike Thermal Processing Using Arc Lamps - D. Camm and M. Lefrancois (Vortek Industries Ltd) PDF
3:30568 Novel High Ramp-Down Rate and Reflector Design in Rapid Thermal Process - M.H. Lee and C. Liu (National Taiwan University) GIF
3:50569 Improved Performance of a Fast-Ramp RTA System through Recipe and Controller Optimization - D. de Roover (SC Solutions, Inc.), S. Ramamurthy, A. Mayur (Applied Materials, Inc.), and J. Ebert (SC Solutions, Inc.) PDF