199th Meeting - Washington, DC

March 25-30, 2001


N2 - Rapid Thermal and Other Short-Time Processing Technologies II

Electronics Division/ Dielectric Science and Technology Division/ High Temperature Materials Division

Monday, March 26, 2001

West Salon B, Ballroom Level

Advanced Thermal Processing Equipment and Process Monitoring I

Co-Chairs: J.C. Gelpey and F. Roozeboom

10:00557 Single Wafer Thermal Processing for 300 mm Semiconductor Manufacturing - Y. Ma (Bell Labs - Lucent Technologies) PDF
10:30558 Emissivity Effects in Differential Epitaxial Growth (DEG) - E. Aksen, W. de Boer, and D. Terpstra (Philips Research Laboratories) PDF
10:50559 Fast-Ramp, Low-Temperature Annealing in the Levitor Floating Wafer System - E. Granneman, V. Kuznetsov, A. Storm (ASM International nv), J. Post (Philips CFT), T. Ritzdorf, B. Weaver, and R. Baskaran (Semitool) PDF
11:20560 An RTP Chamber Model for Emissivity - B. Adams and A. Hunter (Applied Materials) PDF
11:40561 Concept of Electrically Switchable Reflector Films on the Chamber Walls of RTP Reactors - F. Roozeboom, P. van der Sluis, and N. Cowern (Philips Research) PDF

Advanced Thermal Processing Equipment and Process Monitoring II

Co-Chairs: P.J. Timans and Y. Ma

2:00562 Non-destructive Post-Anneal Characterization of Source/Drain Processes using the Carrier Illumination^(TM) Method - P. Borden and L. Bechtler (Boxer Cross Inc) PDF
2:30563 Hot Wall RTP for Thin Gate Oxide and Silicon Nitride - Y. Senzaki, J. Sisson, R. Herring, J. Yao, D. Teasdale, and J. Ricketts (SVG Thermal Systems) PDF
2:50564 Characterization of Ultra Thin Gate Dielectrics by Grazing X-Ray Reflectance and Spectroscopic Ellipsometry on the Same Instrument - J.L. Stehle, P. Boher, C. Defranoux, S. Bourtault, P. Evrard, and J.P. Piel (SOPRA S.A.) PDF
3:20565 Analysis of Pinmark Induced Defects After RTP - J. Niess, W. Dietl, O. Altug, W. Lerch (STEAG RTP Systems GmbH), H.D. Geiler, and H. Karge (Jenawave) PDF
3:40 Twenty-Minute Intermission

Gate Engineering

Co-Chairs: M.L. Green and P.J. Timans

4:00566 Implant and Anneal Methods for PMOS Gates - A. Fiory and K. Bourdelle (Bell Laboratories, Lucent Technologies, Inc.) PDF
4:20567 Electrical and Material Characterization of Uniform Very-Heavily Doped P+ Polysilicon Films Deposited by RTCVD - W. Kiether, D. Hodge, and J. Hauser (North Carolina State University) PDF
4:40568 The Effect of Deposition Temperature on Grain Structure and Electrical Properties of Amorphous and Polycrystalline Silicon Fabricated by Rapid Thermal Chemical Vapor Deposition for the Application of CMOS Gate Electrodes - Y. Chen, Y. Ma (Bell Labs - Lucent Technologies), and W.H. Koh (Charted Semiconductor) PDF
5:00569 Dry Oxidation and Implant Anneal in a Single Wafer Rapid Thermal Furnace - T. Fukada, W.S. Yoo, Y. Hiraga, K. Kang (WaferMasters, Inc.), and H. Kitayama (Tokyo Electron Yamanashi Ltd.) PDF
5:20570 RF and Microwave Annealing for Ultra-shallow Junction Formation - K. Thompson, J. Booske, Y. Gianchandani, and R. Cooper (University of Wisconsin) PDF

Tuesday, March 27, 2001

Gate Stacks for Nanoscale CMOS I

Co-Chairs: K. Reid and H.R. Huff

9:00571 The Science of Ultra Thin Gate Oxides for Microprocessor Technology - R. Arghavani (Intel Corporation) PDF
9:30572 Multiple Spike RTP Process for Forming Ultra-Thin Oxides for MOS Gate Dielectric Applications - D. Das (STEAG RTP Systems), J. Jia (Integrated Device Technology, Inc.), A. Daniel, R. Thakur, S.P. Tay (STEAG RTP Systems), and J. Choi (Integrated Device Technology, Inc.) PDF
9:50573 Comparison of Interface Properties of Dry and Wet Oxides Grown in Different Ambients - R. Sharangpani and S.-P. Tay (Steag RTP Systems) PDF
10:10574 Incorporation of Nitrogen into Ultrathin (<2.0 nm) Rapid Thermal Silicon Oxynitrides - M.L. Green, T. Sorsch, W. Gladden, Y. Ma (Lucent Technologies), W.N. Lennard (University of Western Ontario), K. Queeney (Smith College), R. Opila, A. Kerber, T. Nigam, B. Weir, and P. Silverman (Lucent Technologies) PDF
10:30 Twenty-Minute Intermission
10:50575 High-K Gate Dielectrics: ZrO2, HfO2, and Their Silicates - J. Lee, R. Nieh, B.H. Lee, L. Kang, K. Onishi, Y. Jeon, E. Dharmarjan, S. Gopalan, C.S. Kang, and R. Choi (University of Texas at Austin) PDF
11:20576 Preparation of sub 20A thick Ultra-thin Stack Gate Dielectrics by in-situ RT CVD Processes - J. Jeon (AMD) PDF
11:40577 Low Thermal Budget Processing for Silicon Nitride - T.C. Ang and B. Ramachandran (Chartered Semiconductor Manufacturing) PDF

Gate Stacks for Nanoscale CMOS II

Co-Chairs: D.-L. Kwong and R. Arghavani

2:00578 Ultrathin High-K Dielectrics Grown by Atomic Layer Chemical Vapor Deposition (ALCVD): A Comparative Study of ZrO2, HfO2, Y2O3 and Al2O3 - E. Gusev, E. Cartier, D. Buchanan (IBM T.J. Watson Research Center), M. Gribelyuk (IBM Analytical Services), M. Copel, H. Okorn-Schmidt, C. D'Emic, and P. Kozlowski (IBM T.J. Watson Research Center) PDF
2:30579 Physical Characterization of ZrO2 Films on Silicon after Rapid Thermal Anneal - Y.Z. Hu and S.-P. Tay (Steag RTP Systems) PDF
2:50580 Characteristics of Ultra Thin (EOT<10A) RTCVD Zr Silicate (Zr27Si10O63) Gate Dielectrics - C.H. Lee, H.F. Luan, W.P. Bai, S.J. Lee, T.S. Jeon, and D.L. Kwong (The University of Texas at Austin) PDF
3:10581 Device Fabrication and Evaluation of Alternative High-K Dielectrics and Gate Electrodes Using A Non-Self Aligned Gate Process - I. Kim, S. Han, and C. Osburn (North Carolina State University) PDF
3:30 Twenty-Minute Intermission
3:50582 An Annealing Study of La and Zr Silicate-Based Gate Dielectrics - A. Kingon, J.-P. Maria, D. Wicaksana, and J. Parette (North Carolina State University) PDF
4:20583 High Quality Ultra Thin HfO2 Gate Stack Prepared by in-situ RT-MOCVD process - S. Lee, H.F. Luan, W.P. Bai, C.H. Lee (University of Texas at Austin), Y. Senzaki, D. Roberts (Schumacher), L. Myers (University of the West Indies), and D.L. Kwong (University of Texas at Austin) PDF
4:40584 Effect of Postdeposition Rapid Thermal Annealing of Thin (1-x)Ta2O5-xTiO2 Films Formed by Metalorganic Decomposition - K.M.A. Salam, H. Konishi, M. Mizuno, H. Fukuda, and S. Nomura (Muroran Institute of Technology) PDF

Wednesday, March 28, 2001

Thermal Budget Issues

Co-Chairs: F. Roozeboom and W. Lerch

10:00585 Will Thermal Budget Really Matter in the Future? - S. Butler, A. Jain, and D. Mercer (Texas Instruments) PDF

Panel Discussion (10:30 AM - 12:00 Noon)

Co-Chairs: D.-L. Kwong and M.C. Ozturk

10:30 Thermal Budget and Other Challenges in 300 mm Thermal Processing. Panelists: R. Arghavani (Intel), S. Butler (TI), J.C. Gelpey (Steag RTP Systems), E. Granneman (ASMI), H.R. Huff (SEMATECH), Y. Ma (Lucent-Bell Labs.) and K. Reid (Motorola).

Ultra-Shallow Junctions for Nanoscale CMOS I

Co-Chairs: W. Lerch and M.C. Ozturk

2:00586 The Gate Stack / Shallow Junction Challenge for Sub-100 nm Technology Generations: Shallow Junction Emphasis - H.R. Huff, G.A. Brown, and L.A. Larson (International SEMATECH, Inc.) PDF
2:30587 Source/Drain Extensions formed by ImpulseIM Anneal - D. Camm, S. McCoy, M. Lefrancois (Vortek Industries Ltd), and K. Elliott (Vortek Industries Ltd.) PDF
2:50588 Ultra-Shallow Junction Formation by Thermal Diffusion of Surface Deposited Boron into High Energy Ion Pre-Irradiated Si - L. Shao, X. Lu, X. Wang, I. Rusakova, J. Liu, and W.-K. Chu (University of Houston) PDF
3:10589 Fundamental Issues in Rapid Thermal Annealing (RTA), Spike RTA and Excimer Laser Annealing (ELA) for the Formation of Shallow P+/n Junctions - Y.F. Chong, K.L. Pey, A.T.S. Wee (National University of Singapore), A. See (Chartered Semiconductor Manufacturing Ltd.), C.-H. Tung, R. Gopalakrishnan (Institute of Microelectronics), and Y.F. Lu (National University of Singapore) PDF
3:30 Twenty-Minute Intermission

Ultra-Shallow Junctions for Nanoscale CMOS II

Co-Chairs: M.C. Ozturk and S. Butler

3:50590 State of the Art Techniques for Ultra-Shallow Junction Formation - W. Lerch, B. Bayha (STEAG RTP Systems GmbH), D.F. Downey, and E.A. Arevalo (Varian Semiconductor Equipment Associates) PDF
4:20591 Shallow Junction Formation by Small Cluster Implantation - X. Lu, X. Wang, L. Shao, Q. Chen, J. Liu, W.-K. Chu (University of Houston), and P. Ling (Advanced Materials Engineering Research, Inc.,) PDF
4:40592 Quantum Mechanical Modeling and Simulation of Laser Thermal Processing of Heavily B-Doped Si - L. Wang, R. Yu, M.O. Thompson, and P. Clancy (Cornell University) PDF
5:00593 Rapid Thermal Laser Processing: Quantification and Process Integration - M. Thompson, S. Yang (Cornell University), and S. Talwar (Verdant Technologies) PDF
5:30594 A Low-Pressure, Hot-Wall Rapid Thermal Anneal For Next Generation Ultra Shallow Junction Applications - V. Parihar, A. Atanos, and J. Kim (Mattson Technology, Inc.) PDF

Thursday, March 29, 2001

Contacts for Nanoscale CMOS

Co-Chairs: M.C. Ozturk and K. Reid

9:00595 Comparative Study of Reaction and Electrical Properties of Metal/SiGe Contacts for Sub-100nm CMOS Technology - J. Liu, H. Mo, and M. Ozturk (North Carolina State Univeristy) PDF
9:20596 High Thermal Stability Ni/Co Silicide on SiGe for Raised Source/Drain Structures - D. Tweet, J.-S. Maa, and S.T. Hsu (Sharp Laboratories of America) PDF
9:40597 Formation of Nickel Silicide in a Susceptor-based, Low-pressure RTP System - A. Atanos, K. Reddy, A. Dauz, and V. Parihar (Mattson Technology, Inc.) PDF
10:00 Twenty-Minute Intermission

Novel Devices and Applications

Co-Chairs: P.J. Timans and A.F. Fiory

10:20598 The Vertical Replacement-Gate (VRG) MOSFET: A High-Performance Vertical MOSFET with Lithography-Independent Critical Dimensions - J.M. Hergenrother (Bell Laboratories, Lucent Technologies), S.-H. Oh (Stanford University), T. Nigam, D. Monroe, F.P. Klemens, A. Kornblit, F.H. Baumann, J.L. Grazul, R.W. Johnson, C.A. King, and R.N. Kleiman (Bell Laboratories, Lucent Technologies) PDF
10:50599 Realization of Deep P+ Zones by Al Thermomigration in a Temperature Gradient RTP Furnace - B. Morillon (STMicroelectronics), J.-M. Dilhac, C. Ganibal (LAAS-CNRS), and C. Anceau (STMicroelectronics) PDF
11:10600 Spin-on-Glass Bake and Cure using a Resistively Heated Batch Annealing Oven - W.S. Yoo, T. Fukada, Y. Hiraga, K. Kang (WaferMasters, Inc.), and J. Yamamoto (Hiroshima NEC Ltd.) PDF
11:30601 High Performance SOI CMOS Technology: FEOL Process, Device, and Material Interactions - M. Mendicino (Motorola) PDF
12:00602 Metal-Oxide-Silicon Light Emitting Diodes Prepared by Rapid Thermal Oxidation - C.W. Liu, Y.-H. Liu, C.H. Lin, M.H. Lee, M.-J. Chen, and C.-F. Lin (National Taiwan University) PDF