207th ECS Meeting - Quebec City, Canada

May 15 - May 20, 2005

PROGRAM INFORMATION
 

K1 - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment

Electronics and Photonics/Dielectric Science and Technology/High Temperature Materials
 

Monday, May 16, 2005

Room 2000B, Level 2, Quebec City Convention Center

Ultra Shallow Source/Drain Junctions in Silicon

Co-Chairs: P. Timans & S. Felch
TimeAbs#Title and Authors
10:00 612 Electrical Activation and Dopant Diffusion of Heavily Boron Implanted Silicon J. Harnish, C. Carson (Micron Technology, Inc.), J. Foggiato, K. Kang and W. Yoo (WaferMasters, Inc.)
10:20 613 Using Surface Chemistry for Defect Engineering in Ultrashallow Junction Formation E. Seebauer (University of Illinois)
10:50 614 Effect of Amorphization on Activation and Deactivation of Boron in Source/drain, Channel and Poly Gate B. Pawlak, R. Duffy (Philips Research Leuven) and T. Janssens (IMEC)
11:10 615 Ultraviolet Raman Spectroscopic Study on Flash-Anneal Recrystallization of Ultra-Shallow Boron-Implanted Layer on Silicon M. Yoshimoto, H. Nishigaki, H. Harima (Kyoto Institute of Technology), K. Kang and W. Yoo (WaferMasters, Inc.)
11:30 616 Plasma Doping B. Mizuno (Ultimate Junction Technologies Inc.), Y. Sasaki and H. Ito (UJTLab)
 

Advanced CMOS Devices- A Tutorial from Practical Options to Innovative Concepts

Co-Chairs: F. Roozeboom
TimeAbs#Title and Authors
14:00 617 Advanced CMOS Devices- A Tutorial from Practical Options to Innovative Concepts. Part I- Conventional Devices and Technology Options H. Wong (Stanford University)
14:30 618 Advanced CMOS Devices: A Tutorial from Practical Options to Innovative Concepts. Part II- Exploratory Devices and Approaches H. Wong (Stanford University)
15:00 Intermission (20 Minutes)
 

High-K Dielectrics on Silicon

Co-Chairs: E. Gusev & J. Gelpey
TimeAbs#Title and Authors
15:20 619 High-k Gate Stack Engineering Towards Meeting Low Standby Power and High Performance Targets S. De Gendt (IMEC)
15:50 620 On Location and Magnitude of Trapped Charge in Poly-Si ALD-Al2O3 Capped Hf-Silicate Gate Stacks K. Maitra (North Carolina State University), B. Linder (IBM T.J Watson Center, IBM Corp.), E. Gusev (IBM T.J. Watson Research Center, IBM Corp.) and M. Frank (IBM T.J Watson Center, Yorktown Heights)
16:10 621 Thin HfxTiySizO Films with Varying Hf to Ti Contents as Candidates for High-k Dielectrics A. Bauer (Fraunhofer IISB), A. Paskaleva (Institute of Solid State Physics) and M. Lemberger (Chair of Electron Devices)
16:30 622 Properties of HfTaxOy High-K Layers Deposited by ALCVD C. Zhao (IMEC), Z. Rittersma (Philips Leuven), J. Van Berkum, J. Snijders, A. Hendriks, P. Breimer, P. Graat (Philips Research), J. Maes, H. De Witter (ASM Belgium), V. Afanas'ev (University Leuven), E. Tois, M. Tuominen (ASMM), M. Caymax, S. De Gendt and M. Heyns (IMEC)
16:50 623 Properties of the Interfacial Layer in the High-k Gate Stack and Transistor Performance G. Bersuker, J. Peterson, J. Barnett, J. Sim, R. Choi (SEMATECH), B. Lee (IBM assignee at SEMATECH), P. Lysaght and H. Huff (SEMATECH)
17:10 624 CVD of Hafnium Silicate thin films for Advanced Gate Applications R. Sharangpani, S. Muthukrishnan, S. Kher, P. Narwankar, T. Goyani, K. Ahmed and Y. Ma (Applied Materials)
17:30 625 1/f Noise Performance of n-MOSFETs with Hf-based Gate Dielectrics P. Srinivasan (New Jersey Institute of Technology), E. Simoen, L. Pantisano, C. Claeys (IMEC) and D. Misra (New Jersey Institute of Technology)
17:50 626 Effect of Precursor Pulse Time on Charge Trapping and Mobility of ALD HfO2 M. Akbar (University of Texas at Austin), N. Moumen (SEMATECH, IBM assignee), J. Peterson, J. Barnett (SEMATECH), M. Hussain (SEMATECH and The University of Texas at Austin) and J. Lee (University of Texas at Austin)
 

Tuesday, May 17, 2005

Room 2000B, Level 2, Quebec City Convention Center

Advanced MOS Gate Electrodes

Co-Chairs: F. Roozeboom & S. De Gendt
TimeAbs#Title and Authors
08:00 627 The Enhancement of Poly Activation by Laser Annealing Y. Chen, A. Jain, D. Mercer, J. Hu (Texas Instruments), J. Hebb, D. Upadhyaya and Y. Wang (Ultratech Inc.)
08:20 628 Pulsed Excimer Laser Annealing For Meeting Near-Term Front End Processes Gate-Stack Challenges H. Wong (University of California), H. Takeuchi, A. Padilla, T. King (EECS, UCB), M. Ameen (Axcelis Technologies Inc.) and A. Agarwal (Axcelis Technologies Inc)
08:40 629 Metal Wert Etch Process Development For Dual Metal Gate CMOS Using Standard Industry Tools M. Hussain (SEMATECH and The University of Texas at Austin), N. Moumen (SEMATECH, IBM assignee), J. Barnett (SEMATECH), J. Saulters, D. Baker (ATDF), M. Akbar (University of Texas at Austin) and Z. Zhang (SEMATECH, Texas Instrument assignee)
09:00 630 Gate Work Function Modification Using Ultra-Thin Metal Interlayers H. Alshareef, K. Choi, H. Wen (SEMATECH), R. Harris (AMD assignee at SEMATECH), H. Luan (Infineon assignee at SEMATECH), P. Lysaght (SEMATECH), P. Majhi (SEMATECH, Intel assignee) and B. Lee (IBM assignee at SEMATECH)
09:20 631 Atomic Vapor Deposition of Ru and RuO2 Thin Film Layers for Metal Gate Applications C. Manke, O. Boissiere, P. Baumann, J. Lindner and M. Schumacher (Aixtron AG)
09:40 Intermission (30 Minutes)
10:10 632 Tantalum-based Gate Electrode Metals for Advanced CMOS Applications J. Hooker, R. Lander, F. Cubaynes (Philips Research Leuven), T. Schram (IMEC), F. Roozeboom, J. van Zijl, M. Maas, E. van den Heuvel, E. Naburgh, J. van Berkum, Y. Tamming, T. Dao (Philips Research Laboratories), K. Henson, M. Schaekers, A. Ammel, Z. Tokei, M. Demand (IMEC) and C. Dachs (Philips Research Leuven)
10:40 633 Materials Issues of Ni Fully Silicided (FUSI) Gates for CMOS Applications J. Kittl (Texas Instruments), A. Lauwers (IMEC), M. van Dal (Philips Research Leuven), C. Demeurisse, K. Anil, A. Veloso, M. Pawlak, J. Cunniffe, T. Schram, R. Verbeeck, V. Christa, S. Kubicek and K. Maex (IMEC)
11:00 634 Self-aligned PtSi Fully Silicided (FUSI) Metal Gates for 45 nm CMOS Applications M. van Dal (Philips Research Leuven), A. Lauwers, J. Cunniffe, R. Verbeeck, C. Vrancken, C. Demeurisse, J. Kittl and K. Maex (IMEC)
11:20 635 Influence of Activation Annealing and Silicidation Process on Dopant Redistribution and Pile-up at the NixSiy/SiO2 Interface M. Pawlak (IMEC), J. Kittl (Texas Instruments), T. Janssens, A. Lauwers, W. Vandervorst, A. Kottantharayil, T. Schram, A. Veloso (IMEC), M. van Dal (Philips Research Leuven), K. Maex (IMEC) and A. Vantomme (Katholieke Universiteit)
11:40 636 Study of Stress Evolution during Full Silicidation for Gate Stacks C. Torregiani (IMEC), J. Kittl (Texas Instruments) and K. Maex (IMEC)
 

MOS Gate Stacks with High-K Dielectrics and Metal Gate Electrodes

Co-Chairs: D.L. Kwong & H. Iwai
TimeAbs#Title and Authors
14:00 637 New Materials, Processes and Device Structures for 65nm CMOS Technology Node and Beyond B. Nguyen, A. Thean, D. Zhang, T. White, M. Sadaka, D. Triyoso, J. Schaeffer, B. Goolsby, T. Nguyen, V. Dhandapani, V. Vartanian, L. McCormick, D. Theodore, S. Zollner, Q. Xie, X. Wang, Z. Shi (Freescale Semiconductor), L. Mathew (Freescale), M. Zavala, C. Parker, H. Collard, J. Hildreth, L. Prabhu, R. Rai, S. Murphy, P. Montgomery, S. Kalpat, M. Ramon, D. Gilmer, B. Taylor, A. Demkov, V. Adams, J. Jiang, J. Chen (Freescale Semiconductor), C. Chang (TSMC), V. Kaushik, L. Chandna, M. Sadd, A. Barr, A. Vandooren, D. Pham, M. Mendicino, J. Cheek, H. Tseng, B. White, P. Tobin, M. Orlowski, S. Venkatesan, V. Kolagunta, J. Mogab, M. Canonico and M. Kottke (Freescale Semiconductor)
14:30 638 Metal Gated Self-aligned Gate-forward nMOSFET with 0.8 nm EOT Fabricated by In-situ Ar/O2 Plasma Oxidation of PVD Hf S. Koveshnikov (University of Texas at Austin), W. Tsai (Intel Corporation), M. Zhang, C. Choi and J. Lee (University of Texas at Austin)
14:50 639 ALD of Advanced High-k and Metal Gate Stacks for MOS Devices Y. Senzaki, J. Gutt, G. Brown (SEMATECH), P. Kirsch (SEMATECH, IBM assignee), H. Alshareef, K. Choi, C. Huffman, H. Wen (SEMATECH), P. Majhi (SEMATECH, Intel assignee), B. Lee (IBM assignee at SEMATECH), H. Chatham (AvizaTechnology), S. Park (SEMATECH) and S. Lanee (Aviza Technology)
15:20 640 Improving CMOS Performance by AVD Grown High-k Dielectrics and Advanced Metal Electrodes U. Weber, O. Boissiere, J. Lindner, M. Schumacher, P. Lehnen, C. Manke (Aixtron AG), S. Van Elshocht, M. Caymax (IMEC), V. Cosnier (STMicroelectronics) and T. McEntee (AIXTRON AG)
15:40 Intermission (30 Minutes)
16:10 641 New Developments in Schottky Source/Drain High-k/Metal Gate CMOS Transistos M. Li (National University of Singapore), S. Lee (ECE Dept, National University of Singapore), S. Zhu (Microelectronic Dept, Fudan University), R. Li, J. Chen (ECE Department, National University of Singapore) and D. Kwong (ECE Department, University of Texas, Austin)
16:40 642 Nb and NbN Metal Gates for Gate Stacks with High-k Dielectrics M. Schmidt (German Federal Armed Forces University Munich), A. Ludsteck (Universitaet der Bundeswehr Muenchen), F. Wiest (KETEK), J. Schulze and I. Eisele (Universitaet der Bundeswehr Muenchen)
17:00 643 Electron Mobility Dependence of W/HfO2 Gate Stacks on Interfacial Layer Preparation A. Callegari (IBM), P. Jamison (IBM Microelectronics), S. Zafar, D. Lacey, R. McFeely (IBM T.J. Watson Research Center), J. Shepard (IBM Microelectronics), E. Gusev (IBM T.J. Watson Research Center, IBM Corp.), E. Cartier and R. Jammy (IBM T.J. Watson Research Center)
17:20 644 Structural and Electrical Properties of CVD-WNx Thin Films Deposited on High-K Materials S. Allegret (CEA-DRT-LETI (STMicroelectronics assignee)), G. Rolland (CEA-DRT), E. Guidotti (TEL Technology Center America), H. Yamasaki (Tokyo Electron AT), P. Holliger, F. Pierre and F. Martin (CEA-DRT)
 

Room 200A/200B/200C, Level 2, Quebec City Convention Center

Tuesday Evening Poster Session

Co-Chairs: P.J. Timans & L.J. Chen
TimeAbs#Title and Authors
o 645 Electrical Characterization of Doped Hafnium Oxide High-k Films Y. Kuo, J. Yan, S. Chatterjee and J. Lu (Texas A&M University)
o 646 Characterization of Laminated CeO2-HfO2 High-k Gate Dielectrics Deposited by Pulsed Laser Deposition K. Karakaya, A. Zinine (University of Twente), J. van Berkum (Philips Research Laboratories), P. Graat, M. Verheijen, Z. Rittersma (Philips Research), A. Rijnders and D. Blank (University of Twente)
o 647 In-situ Observation of Metal-induced Crystallization of Amorphous Si0.8Ge0.2 Thin Films C. Yu, W. Wu and L. Chen (National Tsing Hua University)
o 648 Characterization of Ultra-Shallow Implanted P+ Layer on P-Type Silicon Substrates after Flash Anneal and Conventional Rapid Thermal Anneal W. Yoo (WaferMasters, Inc.), T. Suzuki, M. Seto, N. Suzuki (Trecenti Technologies, Inc.) and K. Kang (WaferMasters, inc.)
o 649 Interface Formation during Epitaxial Growth of Neodymium Oxide A. Fissel, O. Kirfel, Z. Elassar, E. Bugiel, M. Czernohorsky and H. Osten (University of Hannover)
o 650 Properties of Ru/HfxSi1-xOy/Si MOS Gate Stack Structures Grown by MOCVD K. Frohlich, R. Luptak and K. Husekova (Institute of Electrical Engineering, SAS)
o 651 Thermal Stability of A Novel Graded Layer for Relaxed SiGe/Si Heteroepitaxy L. Wong (Nanyang Technological University), C. Wong, C. Ferraris, T. White (NTU), J. Liu, L. Chan, D. Sohn and L. Hsia (Chartered Semiconductor Manufacturing)
o 652 Ultra Shallow Junction Formation by Flash Annealing: The Challenges Ahead J. Foggiato and W. Yoo (WaferMasters, Inc.)
o 653 Interstitial Oxygen Defect at Si Surface on Electrical Characteristics of High-k Gated MOS Devices K. Chang-Liao (National Tsing Hua University), C. Cheng and T. Wang (National Tsing Hua Uinv.)
o 654 Device Study of Source/Drain Extension and Halo Formation Using a Single-Wafer, High-Current Implanter S. Felch, M. Foad, C. Olsen (Applied Materials Inc.), F. Nouri (Applied Materials), Y. Matsunaga and N. Natsuaki (Applied Materials Inc.)
o 655 High Purity Iridium Thin Films Deposition using an Inorganic Precursor C. Dussarrat (Air Liquide Laboratories) and J. Gatineau (Air Liquide)
o 656 Si:C Epitaxial Wafer for Improved Sub-100nm CMOS Transistor Performance R. Standley (MEMC), M. Mansoori, D. Miles, S. Chakravarthi (Texas Instruments), M. Seacrist (MEMC), R. Wise (Texas Instruments), T. Torack and M. Ries (MEMC)
o 657 Initial Oxidation of Silicon-Germanium Alloy Materials R. Jaccodine (Lehigh University) and S. Kilpatrick (U.S. Army)
o 658 Nickel Thin Film Deposition using NI(PF3)4 for LSI Electrode M. Ishikawa, H. Machida (Trichemical Laboratories Inc.), A. Ogura (Meiji University) and Y. Ohshita (Toyota Technological Institute)
o 659 Investigation of Nitrided Hafnium Silicates for High-κ Dielectrics using Photoelectron Spectroscopy A. Mathew, K. Demirkan, R. Opila (University of Delaware), C. Wang (ASM America) and G. Wilk (ASM America, Phoenix, AZ, USA)
o 660 Suppressed Leakage in Low Temperature RTA (700˚C 30s) Junctions with Buried Epitaxial Si1-yCy C. Tan (National University of Singapore), H. Lee (Chartered Semiconductors), J. Liu (Chartered Semiconductor Manufacturing), E. Quek (Chartered Semiconductors), L. Chan (Chartered Semiconductor Manufacturing) and E. Chor (National University of Singapore)
o 661 Suppression of High Resistance Phases of Nickel Silicide for Sub-100 nm Si CMOS M. Tao, J. Shanmugam and J. Zhu (University of Texas Arlington)
o 662 Charge Trapping in n-MOSFETs with TiN/HfSixOy/SiO2/p-Si Gate Stack during Substrate Injection P. Srinivasan, D. Misra and N. Chowdhury (New Jersey Institute of Technology)
o 663 Short Channel Schottky Barrier TFTs with Metal Gate and High Dielectric Constant Gate Dielectric C. Huang and B. Tsui (National Chiao Tung University)
o 664 Novel Dual Metal Gate Technology Using Mo-MoSix for Advanced MOS Device Applications T. Li, W. Ho (Institute of Electronics, National Chiao Tung University), H. Wang (Taiwan Semiconductor Manufacturing Company) and C. Chang (President Office, National Chiao Tung University)
o 665 Evaluation of Ruthenium Precursors for Thin Film Applications J. Peck (Praxair, Inc.), C. Hoover, D. Thompson, J. Geary and M. Litwin (Praxair)
o 666 ALD Analyses of HfCl4 + O3 and HfCl4 + H2O by Mass Spectroscopy M. Kim (Air Products and Chemicals Korea), S. Rogers (Air Products Asia, Inc.), Y. Kim, J. Lee and H. Kang (Samsung Electronics Co., Ltd.)
o 667 Characteristics of Hf(Si,O) Gate Dielectrics as a Function of HF Content K. Chang, J. Shallenberger (Penn. State University), F. Chang (Taiwan Semiconductor Manufacturing Co.), K. Shanmugasundaram (Penn. State University), P. Roman, P. Mumbauer (Primaxx Inc.) and J. Ruzyllo (Penn. State University)
o 668 Silicon Nitride Material Engineering for Ultra-Shallow Junction Formation J. Gumpher (Tokyo Electron), W. Bather and N. Mehta (Texas Instruments)
o 669 Characterization of the Effect of High k Dielectric Process Conditions on the Performance of Flash Memory by a DOE Method J. Jeon (AMD)
o 670 High Spatial Resolution Mapping of Strain Induced by the Geometry Configuration in Nanoscaled Devices S. Toh, K. Loh (National University of Singapore), C. Boothroyd (Institute of materials research and engineering), K. Li, C. Ang (Chartered semiconductor manufacturing ltd) and L. Chan (Chartered Semiconductor Manufacturing)
o 671 Structural and Electrical Characterization of Zirconium Oxide Thin Films Deposited by MOCVD M. Lisker (Otto-von-Guericke-University of Magdeburg), M. Silinskas, S. Matichyn, R. Dargis (Otto-von-Guericke University of Magdeburg) and E. Burte (Otto-von-Guericke-University of Magdeburg)
o 672 Improvement of Electrical Properties of High-k SrTa2O6 for Gate Dielelectric Applications M. Lisker (Otto-von-Guericke-University of Magdeburg), M. Silinskas (Otto-von-Guericke University of Magdeburg), B. Kalkofen and E. Burte (Otto-von-Guericke-University of Magdeburg)
o 673 Shallow Doping of Silicon from an Adsorbed Phosphorus Surface Layer B. Kalkofen, M. Lisker and E. Burte (Otto-von-Guericke-University of Magdeburg)
 

Wednesday, May 18, 2005

Room 2000B, Level 2, Quebec City Convention Center

MOSFETs with Ge, Strained Si, and Strained SiGe Channels I

Co-Chairs: M.C. Ozturk & C. Lavoic
TimeAbs#Title and Authors
10:00 674 Optimizing Channel Strain and Dislocations in PMOS Transistors with Local Epitaxial SiGe P. Chidambaram, S. Chakravarthy and C. Machala (Texas Instruments)
10:30 675 Suppressed Boron Diffusion in Bulk Silicon below Strained (100) SiGe Surfaces during Nitrogen Annealing M. Carroll (Sandia National Labs), Y. Suh and R. Levy (New Jersey Institute of Technology)
10:50 676 Germanium-on-Si MOSFETs with High-k Gate Dielectrics S. Banerjee (University of Texas), J. Donnelly, J. Chen, S. Joshi, D. Kelly, S. Dey (University of Texas at Austin) and S. Guha (IBM Research Division)
11:20 677 Dopants for N and P Junctions in Germanium A. Satta, M. Meuris, T. Janssens, T. Clarysse, E. Simoen, C. Demeurisse, B. Brijs, I. Hoflijk and W. Vandervorst (IMEC)
11:40 678 High-k Dielectric Growth on Germanium by Atomic Layer Deposition A. Rahtu, M. Tuominen, S. Haukka (ASM Microchemistry Ltd.), K. Ralli and M. Putkonen (Helsinki University of Technology)
 

MOSFETs with Ge, Strained Si, and Strained SiGe Channels II

Co-Chairs: M.C. Ozturk & P.R. Chidambram
TimeAbs#Title and Authors
14:00 679 Strained CMOS Technology with Ge M. Tsai (ERSO/ITRI), P. Chen (ITRI) and M. Lee (ERSO/ITRI)
14:30 680 Strain Effects on Transient Enhanced Diffusion and Deactivation of As Implanted in Si G. Dilliway, A. Smith, J. Hamilton (University of Surrey), L. Xu, P. McNally (Dublin City University), G. Cooke, H. Kheyrandish (MATS UK) and N. Cowern (University of Surrey)
14:50 681 Thermal Processing and Mobility in Strained Heterostructures on Insulator I. Aberg, C. Ni Chleirigh and J. Hoyt (Massachusetts Institute of Technology)
15:20 682 Impact of Recessed S/D SiGe Integration Parameters on Device Performance L. Washington, F. Nouri (Applied Materials), P. Verheyen (IMEC), M. Kawaguchi, Y. Kim, A. Samoilov (Applied Materials), M. Jurczak (IMEC) and V. Moroz (Synopsys, Inc.)
15:40 683 Suppression of Interfacial Reactions in Tungsten /Hafnia /Germanium Structure by Water Vapor Discharge K. Muraoka (Toshiba Corporation)
16:00 Intermission (30 Minutes)
 

Contacts Source/Drain Junctions

Co-Chairs: L. Chen & J. Kittl
TimeAbs#Title and Authors
16:30 684 Highly Scalable PVD/CVD-Cobalt Bilayer Salicidation Technology for sub-50nm CMOSFETs J. Yun, H. Kim, S. Jung, E. Jung (Samsung Electronics), S. Kim, B. Kim (COMTECS), G. Choi, S. Kim, U. Chung and J. Moon (Samsung Electronics)
16:50 685 Reactive Diffusion in the Ni-Si System: Influence of Ni Thickness on the Phase Formation Sequence C. Lavoie (IBM T.J. Watson Research Center), C. Coia (Ecole Polytechnique de Montreal), F. D'Heurle (IBM T.J. Watson Research Center), P. Desjardins (Ecole Polytechnique de Montreal), C. Detavernier (University of Ghent, Belgium) and A. Kellock (IBM Almaden Research Center, CA)
17:20 686 Implementation Issues of Platinum Incorporation for the Improvement of Ni Silicide Morphological Stability V. Carron (Commissariat рам'Energie Atomique), J. Dufourcq (STMicroelectronic) and S. Minoret (CEA/LETI)
17:40 687 The Ni-SiGe Interaction: An Overview; Further Considerations S. Zhang (KTH)