207th ECS Meeting - Quebec City, Canada

May 15 - May 20, 2005

PROGRAM INFORMATION
 

L1 - Symposium on ULSI Process Integration IV

Electronics and Photonics
 

Monday, May 16, 2005

Room 301A, Level 3, Quebec City Convention Center

Process Integration

Co-Chairs: C.L. Claeys & S. Zaima
TimeAbs#Title and Authors
10:10 688 State of the Art in Transistors M. Bohr (Intel)
10:50 689 CMOS Scaling Limit and Nanoelectronics: New materials and processes beyond silicon Y. Nishi (Stanford University)
11:30 690 Logic Based DRAM Technology Evolution Through Ultime Investigation P. Mazoyer, C. Caillat and M. Bouche (STMicroelectronics)
 

Integration of Unit Processes

Co-Chairs: J.O. Borland & F. Gonzalez
TimeAbs#Title and Authors
14:00 691 Atomically Controlled CVD Technology for Future Si-Based Devices J. Murota (Research Institute of Electrical Communication, Tohoku University), M. Sakuraba (Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University) and B. Tillack (IHP microelectronics)
14:30 692 Film Composition and its Profile Control of HfSiON for Poly-Si Gate HfSiON CMOSFET with High Performance and Reliability Y. Tsunashima (Toshiba corporation)
15:00 693 A Review of Si Epitaxy: 40 Years of Progress with an Extraordinary Future D. Meyer (International Recitifier Epitaxial Services)
15:30 694 Surface Preparation and Cleaning Challenges for sub-65nm Process Integration J. Rosato (SCP Global Technologies)
16:00 Intermission (10 Minutes)
16:10 695 Dry Etching of Low-k Dielectrics M. Hori (Nagoya Universigy)
16:40 696 Ultra-low Thermal Budget CMOS Process for 65nm-node Low-Operation-power Applications F. Ootsuka (Selete) and A. Mineji (NEC Electronics)
17:10 697 Infusion Processing : An Alternative to Plasma Technology for Semiconductor Manufacturing J. Hautala (Epion Corporation), W. Skinner, Y. Shao (Epion) and J. Borland (J.O.B Technologies)
 

Wednesday, May 18, 2005

Room 206B, Level 2, Quebec City Convention Center

Gate Stack Integration

Co-Chairs: M. Ostling & D. Sadana
TimeAbs#Title and Authors
10:00 698 Validity of Generated Subordinate Carrier Injection Model in Al-profiled HfAlON Dielectrics H. Satake (MIRAI Project - ASET), H. Ota (MIRAI Project - ASRC), K. Okada, T. Nabatame (MIRAI Project - ASET) and A. Toriumi (The University of Tokyo)
10:30 699 Low-Power and High-Speed Hf-based gated CMOSFET with Poly-Si Gate Electrode T. Iwamoto, T. Ogura (NEC Corporation), M. Terai (NEC), A. Morioka, M. Saitoh (NEC Corporation), N. Kimizuka, Y. Yasuda, K. Imai (NEC Electronics Corporation), S. Fujieda and H. Watanabe (NEC Corporation)
11:00 700 Physical Origins of Mobility Reduction in High-k Gate Transistors S. Saito (Central Research Laboratory, Hitachi, Ltd.)
11:30 701 High-k Dielectrics Integration Prospects S. Kubicek, S. Van Elshocht, A. Delabie (IMEC), K. Yamamoto (Matsushita assignee in IMEC), S. Beckx, M. Claes, N. Van Hoornick (IMEC), D. Kwak, S. Hyun (Samsung assignee in IMEC), A. Rothschild, A. Veloso, K. Anil, G. Lujan (IMEC), J. Kittl (Texas Instruments), A. Lauwers (IMEC), V. Kaushik (Freescale Semiconductor), M. Niwa (Matsushita assignee in IMEC), S. De Gendt, M. Heyns, M. Jurczak and S. Biesemans (IMEC)
 

General Integration Issues

Co-Chairs: C.L. Claeys & F. Gonzalez
TimeAbs#Title and Authors
14:00 702 Applications Focused Trends In SiGe BiCMOS Technologies S. St.Onge, A. Joseph, L. Lanzerotti, N. Feilchenfeld, D. Coolbaugh, B. Orner, J. Dunn and D. Harame (IBM)
14:30 703 Fully Silicided (FUSI) Gate Technology as a Metal Gate Option for Advanced CMOS E. Gusev (IBM T.J. Watson Research Center, IBM Corp.), C. Cabral, Y. Kim (IBM T.J. Watson Research Center), B. Linder (IBM T.J Watson Center, IBM Corp.), E. Cartier, S. Zafar (IBM T.J. Watson Research Center), P. Jamison, H. Nayfeh and S. Fang (IBM Microelectronics)
15:00 704 Optically Probing Damascene Cu Seed and Core for Smoothness and Grain-sizing G. Knight (Ottawa-Carleton Institute of Physics) and T. Smy (Carleton University, dept. of Electronics)
15:20 705 High Density Remote Plasma Enhanced Atomic Layer Deposition of Ruthenium Thin Films M. Ko, E. Lee and J. Park (Hanyang University)
15:40 Intermission (10 Minutes)
15:50 706 Challenges for Interconnect of Future CMOS Generations : Implementation of Emerging Processes and Alternative Architectures V. Arnal (STMicroelectronics), L. Gosset, W. Besling (Philips Semiconductors), A. Farcy, L. Chapelon, A. Fuchsmann (STMicroelectronics), J. Vitiello, S. Chhun (Philips Semiconductors), M. Aimadeddine (STMicroelectronics), C. Guedj (CEA-LETI), J. Guillaumond and J. Torres (STMicroelectronics)
16:20 707 N- and P- Type Lateral DMOSFETs Integration and Optimization in an Advance RF Bicmos Technology B. Szelag, D. Muller, J. Mourier, A. Giry, D. Pache and A. Monroy (STMicroelectronics)
 

Thursday, May 19, 2005

Room 206B, Level 2, Quebec City Convention Center

General Integration Issues II

Co-Chairs: D. Buchanan & Y. Nishi
TimeAbs#Title and Authors
08:00 708 Technology and Applications of Silicon-on-Nothing I. Mizushima (Toshiba Corporation), T. Sato (Toshiba) and Y. Tsunashima (Toshiba corporation)
08:30 709 Process Integration on Glass Substrate by CW Laser Lateral Crystallization (CLC) N. Sasaki (Fujitsu Laboratories)
09:00 710 Novel Integration Concepts for SIGE-Based RF-MOSFETS M. Ostling (KTH- Royal Institute of Technology), B. Malm, P. Hellstrom, H. Radamson, C. Isheden, J. Seger, M. von Haartman and S. Zhang (KTH- Royal Insitute of Technology)
09:30 711 Ultra Shallow Dopant Activation Technologies K. Jones, J. Jacques and D. Zeenburg (University of Florida)
10:00 Intermission (10 Minutes)
10:10 712 Planar Bonded Double Gate MOS Transistors Down to Lg = 10nm M. Vinet, T. Poiroux (CEA) and J. Widiez (STMicroelectronics)
10:40 713 Perspectives for Ultra High Density Nonvolatile Data Storage M. Specht, F. Hofmann and M. Staedele (Infineon Technologies)
11:10 714 Integration of HIMOS Flash Memory in a 90nm CMOS Technology J. De Vos, L. Haspeslagh, M. Demand, A. Redolfi, C. Baerts, S. Beckx, F. Vleugels and J. Van Houdt (IMEC)
11:30 715 Retention Characteristics of MONOS Nonvolatile Memories H. Aozasa, I. Fujiwara (Sony Corporation), K. Yamauchi (Sony semiconductor kyushu corporation), K. Koyama and T. Kobayashi (Sony corporation)
 

Strained Silicon Integration

Co-Chairs: M. Bohr & G. Sandhu
TimeAbs#Title and Authors
14:00 716 Exploring Stress Engineering Appraoches for the 45 nm Technology Node V. Moroz and X. Xu (Synopsys, Inc.)
14:20 717 P+/N Junction Formation in Thin Strain Relaxed Buffer Strained Silicon Substrates: the Effect of the Junction Anneal C. Claeys, G. Eneman, E. Simoen, R. Delhougne, P. Verheyen, V. Simons, R. Loo, M. Caymax, K. De Meyer and W. Vandervorst (IMEC)
14:40 718 The Low-frequency Noise in n-MOSFETs on Strained Silicon: Is There Room for Improvement? E. Simoen, G. Eneman, P. Verheyen, R. Delhougne, R. Rooyackers, R. Loo, W. Vandervorst, K. De Meyer and C. Claeys (IMEC)
15:10 719 Strain Engineering for Si CMOS Technology D. Sadana (IBM Research), S. Bedell (IBM), A. Reznicek, J. de Souza (IBM Research), H. Chen (IBM Microelectronics Division) and F. Keith (IBM Research)
15:40 Intermission (10 Minutes)
 

Back-End of Line Integration

TimeAbs#Title and Authors
15:50 720 CMP Technology for 45nm-Node Cu/Low-k Integration S. Kondo (Semiconductor Leading Edge Technologies, Inc.)
16:20 721 Integration of High Aspect Ratio Structures G. Sandhu and F. Gonzalez (Micron Technology, Inc.)
16:50 722 Reliability of Damascene Copper Interconnects K. Ueno (NEC Electronics Corporation), Y. Kakuhara and T. Ishigami (NEC Electronics)
17:20 723 Development of Porous Low-k Interlayer Dielectrics for 45 nm Technology Node T. Kikkawa (Hiroshima University)
17:50 724 Comparision of MOSFET Characteristics Between ALD and MOCVD TiN Metal Gate on Hf Silicate S. Song (Sematech), B. Lee (IBM), Z. Zhang (Texas Instruments), K. Choi (International SEMATECH), S. Bae (Sematech), H. Alshareef (Texas Instruments), P. Majhi (Intel), H. Wen, J. Bennett, B. Sassman and P. Zeitzoff (International SEMATECH)