210th ECS Meeting - Cancun, Mexico

October 29 - November 03, 2006

PROGRAM INFORMATION
 

E2 - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 2: New Materials, Processes, and Equipment

Electronics and Photonics/Dielectric Science and Technology/High Temperature Materials
 

Monday, October 30, 2006

Universal 3, 1st Floor, Expo Center

Ultra-Shallow Source/Drain Junctions

Co-Chairs: W. Lerch and F. Roozeboom
TimeAbs#Title and Authors
10:00 997 Suppressing Layout-Induced Threshold Variations by Halo Engineering V. Moroz and L. Smith (Synopsys, Inc.)
10:20 998 Sheet Resistance Increase of Shallow Doped Silicon during Native Oxidation in Air B. Kalkofen and E. Burte (Otto-von-Guericke-University Magdeburg)
10:40 999 Low-Leakage Ultra-Scaled Junctions in MOS Devices; from Fundamentals to Improved Device Performance R. Duffy, A. Heringa (Philips Research Leuven), J. Loo, E. Augendre and S. Severi (IMEC)
11:10 1000 CVD Delta-Doped Boron Surface Layers for Ultra-Shallow Junction Formation F. Sarubbi, L. K. Nanver and T. L. Scholtes (Delft University of Technology)
11:30 1001 Novel Methods For Ultrashallow Low Resistance Junction Formation S. H. Jain (IBM corporation (B300 3F14-481)), P. Griffin and J. Plummer (Stanford University)
 
Co-Chairs: P. Timans and S. Jain
TimeAbs#Title and Authors
14:00 1002 Leakage Current Characteristics of Ultra-Shallow Junctions formed by B2H6 Plasma Doping H. Sauddin (Tokyo Institute of Technology), Y. Sasaki, H. Ito, B. Mizuno (Ultimate Junction Technologies, Inc.), P. Ahmet (Frontier Collaborative Research Center, Tokyo Institute of Technology), K. Kakushima, N. Sugii, K. Tsutsui and H. Iwai ()
14:20 1003 Understanding Ion Implantation Defects in Germanium A. R. Peaker (University of Manchester), V. Markevich (University of Manchester, UK) and I. Kovačević (Rudjer Boskovic Institute, Zagreb, Croatia)
14:40 1004 Crystal Damage Removal by Flash Annealing W. Lerch, S. Paul, J. Niess (Mattson Thermal Products GmbH), S. McCoy, J. Gelpey (Mattson Technology Canada), F. Cristiano (LAAS-CNRS) and R. Duffy (Philips Research Leuven)
15:00 1005 3D Pattern Effects in RTA Radiative vs Conductive Heating E. H. Granneman (ASM Europe BV), H. Terhorst (ASM Europe), A. Falepin, E. Rosseel (IMEC), K. Verheyden, K. Vanormelingen (ASM Belgium), H. Bourdon and A. Halimaoui (STMicroelectronics)
15:20 1006 Material-Inversion Solid-Phase Epitaxy of p+ Si for Elevated Junctions Y. Civale, L. K. Nanver and H. Schellevis (Delft University of Technology)
15:40 1007 Ultra-Shallow Junctions Formed by Co-Implantation and Sub-Melt Laser Annealing S. B. Felch (Applied Materials), A. Falepin, S. Severi, E. Augendre (IMEC), T. Noda (Matsushita Electric Industrial Co.), V. Parihar (Applied Materials), F. Nouri (Applied Materials Inc), T. Hoffmann (IMEC), B. Pawlak (Philips Research Europe), P. Eyben, W. Vandervorst (IMEC), S. Thirupapuliyur (Applied Materials) and R. Schreutelkamp (Applied Materials Inc)
 

Contacts to Ultra-Shallow Junctions

Co-Chairs: S. Felch and M. C. Ozturk
TimeAbs#Title and Authors
16:20 1008 Iridium Silicide: a Promising Electrode for Metallic Source/Drain in Decananometer MOSFETs G. Larrieu, E. Dubois, X. Wallart (IEMN) and J. Katcki (Institute of Electron Technology)
16:40 1009 Tuning the Schottky Barrier Height for Future CMOS Z. Zhang and S. Zhang (Royal Institute of Technology)
17:00 1010 Influence of Alloying Elements on the Formation and Stability of NiSi C. Detavernier, D. Deduytsche (Ghent University), J. Jordan-Sweet and C. Lavoie (IBM Research)
17:20 1011 Study of Ni-Silicide Contacts to Si:C Source/Drain. S. Mertens (Imec), Y. Cho (Applied Materials), F. Nouri, R. Schreutelkamp (Applied Materials Inc), Y. Kim (Applied Materials), P. Verheyen, J. Steenbergen, C. Vrancken, H. Bender, O. Richard (Imec), B. Van Daele (IMEC Kapeldreef 75 B3001 Leuven Belgium), W. Vandervorst, P. Absil, S. Kubicek, C. Demeurisse, Z. Tokei and A. Lauwers (IMEC)
17:40 1012 Texture in Nickel-Silicide Films on Silicon P. Alippi (CNR) and A. Alberti (CNR-IMM)
 

Tuesday, October 31, 2006

Universal 3, 1st Floor, Expo Center

Advanced Gate Stacks

Co-Chairs: V. Misra and H. Iwai
TimeAbs#Title and Authors
08:10 1013 Evolution of Structural and Electrical Properties of Plasma Nitrided Silicon Oxynitrides During the Formation Process O. Storbeck (Qimonda GmbH & Co. OHG)
08:30 1014 Effect of Deposition Temperature on Thermal Stability of Lanthanum Oxide/Si Interfacial Transition Layer H. Nohira (Musashi Institute of Technology), T. Matsuda (Department of Electrical & Electronic Engineering, Musashi Institute of Technology), K. Tachi, Y. Shiino, J. Song, Y. Kuroki, J. Ng, P. Ahmet (Frontier Collaborative Research Center, Tokyo Institute of Technology), K. Kakushima, K. Tsutsui (Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology), E. Ikenaga, K. Kobayashi, H. Iwai and T. Hattori (FCRC, Tokyo Institute of Technology; ARL, Musashi Institute of Technology)
08:50 1015 Control of Material Interactions in Advanced High-k Metal Gate Stacks C. Wajda, G. Leusink (TEL Technology Center, America), K. Akiyama, S. Ashigaki, S. Aoyama, K. Shimomura, M. Aruga, T. Takahashi, K. Yamazaki and H. Yamasaki (Tokyo Electron AT)
09:20 1016 Thermal Stability of HfN Compounds on HfO2/SiO2 Gate Stacks A. Callegari (IBM, T J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York, 10598), M. Gribelyuk (IBM SRDC East Fishkill) and A. Kellock (IBM Almaden)
09:40 Intermission (20 Minutes)
10:00 1017 On the Growth of Native Oxides on Hydrogen-Terminated Silicon Surfaces in Dark and Under Illumination with Light A. Y. Kovalgin, A. Zinine, R. Bankras, H. Wormeester, B. Poelsema and J. Schmitz (MESA+ Institute for Nanotechnology, University of Twente)
10:20 1018 Low Temperature Silcore a-Silicon Deposition P. R. Fischer (ASM Belgium), S. Van Aerde (ASM Belgium N.V.), E. Oosterlaken, B. Bozon and P. M. Zagwijn (ASM Europe B.V.)
10:50 1019 Impact of Grain Size Distribution of Gate Poly-Si on PMOSFET Performance K. Saki (Toshiba Corporation)
11:10 1020 The Stress of Polycrystalline Silicon for the Advanced CMOS Technologies Y. Chen (Texas Instruments Inc.), D. Mercer (Texas Instruments), T. Tran and P. Hester (ADE Corporation)
11:30 1021 Ni, Pt and Yb Based Fully Silicided (FUSI) Gates for Scaled CMOS Technologies J. A. Kittl (Texas Instruments), A. Lauwers (IMEC), M. van Dal (Philips Research Europe), H. Yu, A. Veloso, T. Hoffmann, M. Pawlak, C. Demeurisse, S. Kubicek (IMEC), M. Niwa (Matsushita), C. Vrancken, P. Absil and S. Biesemans (IMEC)
 
Co-Chairs: P. Fischer and D. L. Kwong
TimeAbs#Title and Authors
14:00 1022 Charge Defects, Vt Shifts, and the Solution to the High-K Metal Gate n-MOSFET Problem S. Guha, V. Narayanan, V. Paruchuri, B. Linder, M. Copel, N. Bojarczuk, Y. Kim (IBM Research), M. Chudzik, Y. Wang and P. Ronsheim (IBM)
14:30 1023 NBTI Study on PMOS Devices with TiN/HfO2 Gate Stack and Process Induced Strain A. K. Shickova (IMEC vzw), P. Verheyen, G. Eneman (IMEC), E. San Andres (IMEC vzw), P. Absil (IMEC), B. Kaczer and G. Groeseneken (IMEC vzw)
14:50 Intermission (20 Minutes)
15:10 1024 Challenges in Dual Workfunction Metal Gate CMOS Integration B. Lee, S. Song and R. Jammy (SEMATECH)
15:40 1025 Feasibility of Dipole Based Work Function Tuning for Sub 1nm EOT Metal Gated High-K Stacks V. Misra (NC State University), R. Jha, B. Chen and J. Lee (North Carolina State University)
16:10 1026 Low Pressure Chemical Vapor Deposition of Ta-Based Material K. Yanagita, C. Dussarrat and L. Beyssac (Air Liquide Laboratories)
16:30 1027 Chlorine Controlled High Throughput TiN Process with Space Divided CVD H. Kim (Jusung Engineering Co., Ltd)
17:00 1028 Damascene Metal Gate Technology for Gentle Integration of Crystalline High-K-Gate Dielectrics R. Endres (Darmstadt University of Technology), Y. Stefanov and U. Schwalke (Institute for Semiconductor Technology)
17:20 1029 Thermal/Chemical Stability of ALD Ru-TaN Thin Films for Gate Electrode Applications M. Tungare, S. Kumar and E. Eisenbraun (University at Albany, SUNY)
 

Universal Ballroom, 2nd Floor, Expo Center

Tuesday Evening Poster Session

Co-Chairs:
TimeAbs#Title and Authors
o 1030 Resist Stripping Process on Germanium : a Basic Post-Implant Study L. Lachal, J. Chiaroni and F. Perrin (CEA)
o 1031 Real-Time Observation of Initial Thermal Oxidation on Si(110)-16x2 Surface by Photoemission Spectroscopy M. Suemitsu (Tohoku Univ.), A. Kato, H. Togashi, A. Konno, Y. Yamamoto (Tohoku University), Y. Teraoka, A. Yoshigoe (JAEA) and Y. Narita (Kyushu Institute of Technology)
 

Thursday, November 2, 2006

Universal 3, 1st Floor, Expo Center

Advanced CMOS Channel Engineering: Strained Silicon and Germanium Channels

Co-Chairs: E. Bakkers and M. C. Ozturk
TimeAbs#Title and Authors
08:20 1032 State-of-the-Art Characterisation for 65 nm CMOS Processes and Beyond M. Hopstaken (Philips Semiconductors Crolles R&D), M. Juhel, J. Gonchond (ST Microelectronics), L. Kwakman (Philips Semiconductors Crolles R&D) and C. Wyon (CEA-LETI)
08:40 1033 Fully Depleted Silicon-on-Insulator nMOSFETs with Tensile Strained High Carbon Content Si1-yCy Channel F. Ducroquet (CEA-LETI/CNRS), J. Hartmann, C. Tabone, D. Lafond (CEA-LETI), C. Vizioz (CEA - Léti), T. P. Ernst and S. Deleonibus (CEA-LETI)
09:00 1034 High Mobility Channels for Ultimate CMOS D. Sadana (IBM)
09:30 1035 Laser Spike Annealing of Strained Si/ Strained Si0.3Ge0.7/ Relaxed Si0.7Ge0.3 Dual Channel High Mobility p-MOSFETs C. Ni Chleirigh (MIT), X. Wang, G. Rimple (Ultratech, Inc.), Y. Wang (Ultratech, Inc), M. Canonico (Freescale Semiconductors Inc.), O. Olubuyide and J. L. Hoyt (MIT)
09:50 1036 Dual Substrate Orientation Integration for High Performance (110) PMOS G. Karve, W. Ted, D. Eades (Freescale), M. Sadaka (Coldwatt), G. Spencer, J. Hackenberg, J. Norbert, T. Kropewnicki, S. Zollner (Freescale), P. Beckage (AMD), J. Grant, R. Garcia, B. Nguyen, N. Cave, M. Hall, J. Cheek, S. Venkatesan (Freescale), C. Lin and I. Wu (Taiwan Semiconductor Manufacturing Co.)
10:10 Intermission (20 Minutes)
10:30 1037 Current Challenges in Ge MOS Technology A. Dimoulas (NCSR Demokritos), M. Houssa (IMEC), A. Ritenour (MIT, Cambridge, MA), J. Fompeyrine (IBM Research GmbH Rueschlikon Switzerland), W. Tsai (Intel Corporation), J. Seo (EPFL, Lausanne, Switzerland), Y. Panayiotatos, P. Tsipas (NCSR Demokritos), D. P. Brunco (IMEC vzw), M. R. Caymax (Imec), J. Locquet (IBM Research GmbH Rueschlikon Switzerland) and C. Dieker (EPFL, Lausanne, Switzerland)
11:00 1038 Investigating Electronic and Chemical Properties of Ge/GeOxNy/HfO2 Gate Stacks : High-Resolution Photoelectron Spectroscopy Using Synchrotron Radiation O. J. Renault (CEA-DRT/LETI), E. Martinez, L. Fourdrinier (CEA-Léti), L. Clavelier (CEA - LETI) and N. Barrett (CEA-DRECAM)
11:20 1039 Point-Defect Generation in Ni-, Pd-, and Pt-Germanided Schottky Barriers on N-Type Germanium Substrates E. R. Simoen, K. Opsomer, C. L. Claeys, K. Maex (IMEC), C. Detavernier (Ghent University), R. Van Meirhaeghe (University Ghent), S. Forment and P. Clauws (Ghent University)
 

Advanced CMOS Channel Engineering: 3-D Integration, Nanowires & Compound Semicon

Co-Chairs: D. Sadana and E. Gusev
TimeAbs#Title and Authors
14:00 1040 Can Three-Dimensional Devices Extend Moore's Law Beyond the 32 nm Technology Node? M. Orlowski (Freescale Semiconductor)
14:20 1041 Geometry Dependence of Poly-Si Oxidation and its Application to Self-Align, Maskless Process for Nano-scale Vertical CMOS Structur H. Cho (Stanford University), P. Kapur (Electrical Engineering, Stanfrod University,CA), P. Kalavade (Intel Corporation) and K. Saraswat (Stanford University)
14:40 1042 Epitaxial III-V Nanowires on Silicon for Vertical Devices E. Bakkers (Philips Research Laboratories), M. Borgstrom, W. van den Einden, M. van Weert, A. Helman and M. Verheijen (Philips Research Labs)
15:10 1043 Indium Antimonide Based Quantum Well FETs for Ultra-High Speed Electronics T. Ashley, L. Buckle, M. Emeny, M. Fearn, D. Hayes, K. Hilton, R. Jefferies, T. Martin, T. Phillips, J. Powell, A. Tang, M. Uren, D. Wallis, P. Wilding (QinetiQ), S. Datta and R. Chau (Intel)
15:40 Intermission (20 Minutes)
16:00 1044 III-V Compound Semiconductor MOSFET M. Hong and J. Kwo (National Tsing Hua University)
16:30 1045 Conductive AFM Measurements on Carbon Nanotubes and Application for CNTFET Characterization L. Rispal, T. Ruland, Y. Stefanov, F. Wessely and U. Schwalke (Institute for Semiconductor Technology)
16:50 1046 Electrical Characteristics of Ge-Nanocrystal Embedded MOS Capacitors for Non-Volatile-Memory Application S. Choi (Samsung Electronics Co.,LTD), Y. Park, K. Cho, T. Kang, T. Kim (Samsung Electronics. Co., Ltd.), B. Park, K. Cho and S. Kim (Korea University)