213th ECS Meeting - Phoenix, AZ

May 18 - May 22, 2008

PROGRAM INFORMATION
 

E1 - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 4: New Materials, Processes, and Equipment

Electronics and Photonics/Dielectric Science and Technology/High Temperature Materials
 

Monday, May 19, 2008

Room 101A, 100 Level, Phoenix Convention Center

Keynote Address

Co-Chair(s): F. Roozeboom and E. Gusev
TimeAbs#Title and Authors
10:30   617   The Semiconductor Industry's Nanoelectronics Research Initiative: Motivation and Challenges J. Welser (IBM / SRC)
 

Short-Time Annealing - Dopant Activation and Diffusion

Co-Chair(s): P. Timans and K. Knutson
TimeAbs#Title and Authors
14:00   618   Temperature Profiles During Millisecond Processing D. M. Camm, J. Gelpey, S. McCoy (Mattson Technology Canada Inc.) and G. Stuart (Mattson Technolgoy Canada Inc,)
14:30   619   Impact of Millisecond Laser Anneal on the Thermal Stress- Induced Defect Creation in Si1-xGex Source /Drain Junctions M. Bargallo Gonzalez, E. Simoen, E. Rosseel, P. Verheyen, T. Yves Hoffmann, R. Loo, P. Absil and C. Claeys (IMEC)
14:50   620   In-situ Monitoring of Si Wafer Temperature during Millisecond Rapid Thermal Annealing H. Furukawa, S. Higashi, T. Okada, H. Kaku, H. Murakami and S. Miyazaki (Hiroshima University)
15:10   621   High-Resolution Junction Photo-Voltage Mapping of Sheet Resistance and Leakage Current Variations with Ms-Timescale Annealing Methods V. Faifer, J. Halim, J. Lu (Frontier Semiconductor) and M. I. Current (Current Scientific)
15:30 Intermission (20 Minutes)
 

Dopant Activation and Diffusion

Co-Chair(s): E. Gusev and D. Camm
TimeAbs#Title and Authors
15:50   622   Dopant Activation Phenomenon by Flash Lamp Annealing Y. Nara, S. Kato, T. Aoyama, T. Onizawa and Y. Ohji (Semiconductor Leading Edge Technologies)
16:20   623   Is the Vacancy Engineering Approach suitable for the Control of Dopant Diffusion and Activation in Silicon ? O. Marcelot (CEMES/CNRS), A. Claverie (CMES/CNRS) and D. Alquier (Université de Tours, LMP)
16:40   624   Defect Engineering for Ultrashallow Junctions using Surfaces E. Seebauer, C. Kwok, R. Vaidyanathan, Y. Kondratenko (University of Illinois), S. Yeong, M. Srinivasan (National University of Singapore), B. Colombeau and L. Chan (Chartered Semiconductor Manufacturing Ltd)
17:00   625   Physical Modeling of Layout-Dependent Transistor Performance K. L. Knutson (Intel), S. Cea, M. Giles, P. Keys, P. Davids, C. Weber, L. Shifren, R. Kotlyar, J. Hwang, S. Talukdar and M. Stettler (Intel Corporation)
 

Tuesday, May 20, 2008

Room 101A, 100 Level, Phoenix Convention Center

CMOS Gate-Stack Engineering

Co-Chair(s): F. Roozeboom and V. Narayanan
TimeAbs#Title and Authors
08:50   626   ALD Grown Rare Earth Oxides for Advanced Gate Stack S. Schamm (CEMES), P. Coulon, S. Miao (CEMES-CNRS), L. Lamagna, D. Tsoutsou, S. N. Volkos, G. Scarel and M. Fanciulli (CNR-INFM)
09:20   627   Process Characteristics and Physical Properties of MO-ALD ZrO2 Thin Films Deposited on a 300 mm Deposition System S. Consiglio (TEL Technology Center, America), R. Clark, C. Wajda (Tokyo Electron Technology Center America), M. Igeta (TEL Technology Center, America), G. Leusink (Tokyo Electron Technology Center America), T. Sugawara and H. Nakabayashi (TEL LPDC FEOL Group)
09:40 Intermission (20 Minutes)
10:00   628   Crystalline Structure of HfZrO Thin Films and HfO2 / ZrO2 Bilayers Grown by AVD for MOS Applications S. Lhostis, C. Gaumer (STMicroelectronics), C. Bonafos, S. Schamn (CEMES), F. Pierre, A. Fanton (CEA), C. Morin (STMicroelectronics), X. Garros, M. Casse and C. Leroux (CEA)
10:20   629   High-k/Metal Gates- From Research Lab to Market Reality V. Narayanan (IBM T. J. Watson Research Center)
10:50   630   Investigation of VT Shift Mechanism of Hf-Based Dielectrics caused by Lanthanum Capping for NMOS and Tantalum Capping for PMOS Devices B. Lee, D. Lichtenwalner (North Carolina State University), M. Agustin, R. Arghavani, X. Tang, S. Gandikota (Applied Materials) and V. Misra (North Carolina State University)
11:10   631   Implementation of High-k / Metal Gate in High-Volume Manufacturing R. Arghavani, M. Agustine, K. Ahmed, C. Cheng, S. Gandikota, S. Hung, R. Schreutelkamp and N. Yoshida (Applied Materials)
11:40   632   Enabling Effective Work Function Tuning by RFPVD Metal Oxide on High-k Gate Dielectric N. Yoshida, X. Tang, K. Ahmed, M. Agustin, S. Hung, V. Ku, O. Chan, R. Liang, H. Chen, B. Zheng, G. Conti, C. Lazik, M. Jin, K. Lavu, C. Chang, T. Mandrekar and S. Gandikota (Applied Materials)
 

CMOS Channel Engineering I

Co-Chair(s): D-L. Kwong and P. Majhi
TimeAbs#Title and Authors
14:00   633   Oxidation of Suspended Stacked Silicon Nanowire for Sub-10nm Cross-Section Shape Optimization A. Hubert, J. Colonna, S. Bécu, C. Dupré, V. Maffini-Alvaro, J. Hartmann, S. Pauliac, C. Vizioz, F. Aussenac, C. Carabasse, V. Delaye, T. Ernst and S. Deleonibus (CEA)
14:20   634   Si Nanowire CMOS Transistors and Circuits by Top-Down Technology Approach N. Balasubramanian, N. Singh, S. C. Rustogi, K. D. Buddharaju (Institute of Microelectronics), J. Fu (ECE Department, National University of Singapore), S. Balakumar, L. Guo Qiang and D. Kwong (Institute of Microelectronics)
14:50   635   Key Process Technologies for Fabrication of Sub-15nm FinFET and Reduction of Its Parasitic Resistance H. Kawasaki (Toshiba America Electronic Components Inc.)
15:20 Intermission (20 Minutes)
15:40   636   Material Aspects and Challenges for SOI FinFET Integration (Invited) M. J. Van Dal (NXP Semiconductors), G. Vellianitis (NXP-TSMC Research Centre), R. Duffy, B. Pawlak (NXP Semiconductors), K. Lai (TSMC), A. Y. Hikavyy, N. Collaert, M. Jurczak (IMEC) and R. Lander (NXP-TSMC Research Centre)
16:10   637   Ge Enrichment Technique on SiGe/SOI Mesa Islands: a Localized GeOI Structures Fabrication Method B. Vincent, J. Damlencourt (CEA), Y. Morand (ST Microelectronics), D. Rouchon (CEA-LETI Minatec) and M. Mermoux (INPG)
16:30   638   Growth of Strain InAs-Channel Quantum Well FETs on Si Substrate Using SiGe buffer E. Chang, Y. Lin and S. Tang (National Chiao Tung University)
17:00   639   Nitride Transistors for Beyond-Si Digital Electronics F. Mieville, J. Chung (Massachusetts Institute of Technology), S. Rajan, U. Mishra (University of California - Santa Barbara) and T. Palacios (Massachusetts Institute of Technology)
 

Hall 2, 200 Level, Phoenix Convention Center

Poster Session

TimeAbs#Title and Authors
o   640   High-Quality Nickel Silicide MOS Capacitors Fabricated with a Cl Plasma Containing NiCl F. Hirose, K. Kanomata, T. Suzuki (Yamagata University) and N. Oyama (PhyzChemix Corp.)
o   641   A Study on the Formation Processes and Microstructures of Ni-Silicide Films on epi-Si1-xCx J. Yoo, H. Chang, M. Cho (Yonsei University), T. Lee (Jusung Engineering) and D. Ko (Yonsei University)
o   642   Electrical Characteristics of Low-Temperature Poly-Silicon Thin-Film Transistor Using a Stacked Pr2O3/SiOxNy Gate Dielectric T. Pan, T. Wu, C. Chan and C. Lee (Chang Gung University)
o   643   Electrical and Materials Characterization of HfO2 and ZrO2 Thin Films for High-K Gate Applications Deposited by ALD in a 300 mm Reactor L. F. Edge, P. Jamison, H. Jagannathan (IBM @ Albany NanoTech), B. Linder, J. Bruley, M. Copel, J. Jordan-Sweet (IBM Research Division, T.J. Watson Research Center), R. Murphy (IBM Semiconductor Research and Development Center (SRDC), IBM Systems and Technology Division), V. Narayanan (IBM T. J. Watson Research Center), V. Paruchuri (IBM @ Albany NanoTech), S. Consiglio (TEL Technology Center, America), C. Wajda, G. Leusink and R. Clark (Tokyo Electron Technology Center America)
o   644   Crystallographic Silicon-Etching for Ultra-High Aspect-Ratio FinFET V. Jovanovic, T. Suligoj (University of Zagreb) and L. Nanver (Delft University of Technology)
o   645   Pattern Dependence of Epitaxial-Realignment in Direct Silicon Bonded (DSB) Substrates with Hybrid Crystal Orientation H. Itokawa, A. Nomachi, N. Yasutake, T. Ishida, T. Fukushima, H. Harakawa, Y. Kawase, A. Azuma and I. Mizushima (Toshiba Corporation)
o   646   Hf-Silicidation Reactions due to Vacuum Annealing for Poly-Si/ HfSiO(N)/ SiON/ Si Gate Stack Studied by Photoemission Spectroscopy H. Kamada, T. Tanimura, S. Toyoda, H. Kumigashira, M. Oshima (The University of Tokyo), K. Ikeda, G. Liu and Z. Liu (STARC)
o   647   Application of HCl Etch in the Production of Novel Devices A. Y. Hikavyy, R. Rooyackers, P. Verheyen (IMEC), G. Vellianitis (NXP-TSMC Research Centre), M. J. Van Dal (NXP Semiconductors), R. Lander (NXP-TSMC Research Centre), R. Loo and M. Caymax (Imec)
o   648   Sc Addition in HfO2 Thin Films Prepared by Liquid-Injection MOCVD: Structural and Electrical Characterization V. Brize (INPG-CNRS), F. Terrenoir (STMicroelectronics), N. Rochat (CEA/LETI), B. Holländer (IBN1-IT), B. Feist, N. Blasco (Air Liquide, Centre de Recherche Claude-Delorme, 1 Chemin de la Porte des Loges, BP126, 78354, Jouy-en-Josas, France) and C. Dubourdieu (INPG-CNRS, 3 parvis L. Néel, BP 257 - Grenoble INP - Minatec, France)
o   649   Quantum (5 5 12)Si Nanowire 300K MOSFET D. L. Kendall (University of New Mexico), F. J. De la Hidalga-W (INAOE, Inst. Nal. de Astrofísica, Óptica y Electrónica), R. Rodríguez-M, M. Castro-L, A. Torres-J, W. Calleja-A, E. Meza-P, M. Landa-V, C. Zúñiga-I, R. Murphy-A, N. Carlos-R, I. Juárez-R (INAOE) and M. Kendall (StarMega Corp.)
o   650   Impact on 1/f Noise due to Gate Electrodes in High-κ. Based MOSFETs - A Comparison Study Between Poly-Si Vs Metal Vs FUSI P. Srinivasan (Texas Instruments)
o   651   Electrical Property Improvements of High K Gate Oxide by F Plasma Treatment W. Maeng and H. Kim (POSTECH)
o   652   Atomic-Layer-Deposition of SiO2 with Tris(Dimethylamino)Silane (TDMAS) and Ozone Investigated by Infrared Absorption Spectroscopy F. Hirose, Y. Kinoshita, S. Shibuya (Yamagata University), H. Miya (Hitachi Kokusai Electric Inc), K. Hirahara (Shin-Etsu Chemical), Y. Kimura and M. Niwano (Tohoku University)
o   653   In-Depth Profiles of Chemical States and Charge Density in HfSiON Films Studied by Synchrotron Radiation Photoelectron Spectroscopy T. Tanimura, S. Toyoda, H. Kumigashira, M. Oshima (The University of Tokyo), K. Ikeda, G. Liu and Z. Liu (STARC)
o   654   Chemical Vapor Deposition using Pt(PF3)4 and Ni(PF3)4 M. Ishikawa (Meiji University), I. Muramoto, H. Machida (Tri Chemical Laboratories Inc.), S. Imai, A. Ogura (Meiji University) and Y. Ohshita (Toyota Technological Institute)
o   655   ZrO2 and HfO2 Interface with Silicon: a DFT Study of Stress and Strain Effects G. Giorgi (University of Perugia), A. Korkin (Nano & Giga Solutions) and K. Yamashita (Department of Chemical System Engineering, Graduate School of Engineering, The University of Tokyo)
o   656   Hole Mobility Behavior in Strained SiGe-on-SOI p-MOSFETs T. Shim (Hanyang University), S. Kim (Nano-SOI Process Lab.), J. Baek, H. Lee, G. Lee (Hanyang University), K. Kim, W. Cho (Kwangwoon University) and J. Park (Hanyang University)
o   657   Effect of Thermal Annealing on the Electrical Properties of Thin ZrO2 Layers L. A. Sanchez, N. Nedev (Universidad Autonoma de Baja California), R. K. Zlatev, B. S. Valdez (University of Baja California) and L. Alvarez (Universidad Autonoma de Baja California)
o   658   Transconductance Enhancement by Utilizing Pattern Dependent Oxidation in Silicon Nanowire Field-Effect Transistors A. Seike, T. Tange, I. Sano, Y. Sugiura, I. Tsuchida, H. Ohta, T. Watanabe (Waseda University), D. Kosemura, A. Ogura (Meiji University) and I. Ohdomari (Waseda University)
o   659   Impact of New Approach to Improve RF Power FETs Performance on Si(110) Surface W. Cheng, A. Teramoto and T. Ohmi (Tohoku University)
o   660   Characterization of Process Induced Surface Profiles and Lattice Strains using Optical Surface Profilometry and Multi-wavelength Raman Spectroscopy W. Yoo, T. Ueda, J. Kajiwara, T. Ishigaki and K. Kang (WaferMasters, Inc.)
o   661   The Electrical Properties of Low Temperature Poly-Si Thin Film Transistor using Ni-ALD Process S. Lee, C. Lee, T. Jung and H. Kim (Yonsei University)
o   662   Dual Gate Oxide Electrical Defect Analysis J. M. Towner and J. Naughton (AMI Semiconductor)
o   663   The Study of Workfunction Measurement Method for Bilayer Metal Gate Electrode using XPS E. Jung, C. Yim, I. Yang, S. Cho, D. Ko and M. Cho (Yonsei University)
 

Wednesday, May 21, 2008

Room 101A, 100 Level, Phoenix Convention Center

CMOS Channel Engineering II

Co-Chair(s): H. Iwai and M. van Dal
TimeAbs#Title and Authors
09:00   667   CMOS Scaling for the Next Decade: Trends, Challenges and Opportunities P. Majhi (Sematech, TX)
09:30 Intermission (20 Minutes)
09:50   668   Uniaxially Strained Si/SiGe Wire-Channel Transistors T. Tezuka, T. Irisawa (MIRAI-ASET), E. Toyoda (Covalent Materials Corp.), N. Sugiyama (MIRAI-ASET) and S. Takagi (The University of Tokyo, MIRAI-ASRC)
10:20   669   Performance of Germanium Metal-Insulator-Semiconductor Field Effect Transistors with Nickel Germanide Source/Drain N. Taoka (MIRAI-ASRC), K. Ikeda, T. Yamamoto, Y. Yamashita, M. Harada, N. Sugiyama (MIRAI-ASET) and S. Takagi (The University of Tokyo, MIRAI-ASRC)
10:50   670   Throughput Considerations for In-Situ Doped Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices M. Bauer, Y. Zhang, P. Brabant, D. Weeks, V. Machkaoutsan and S. G. Thomas (ASM America Inc.)
11:20   671   Critical Analysis of Different Techniques for Measuring Strain in Si1-yCy Layers Grown by CVD on a Si Substrate N. Cherkashin (CEMES-CNRS), A. Gouye (CEA-LETI), F. Hue, F. Houdellier, M. Hytch (CEMES-CNRS), O. Kermarrec (STMicroelectronics), D. Rouchon, M. Burdin, P. Holliger (CEA-LETI Minatec) and A. Claverie (CMES/CNRS)
11:40   672   Heavily Phosphorus Doped Silicon Junctions for nMOS Applications S. Chopra, Z. Ye, A. Zojaji, Y. Kim and S. Kuppurao (Applied Materials)
 

CMOS Source/Drain Contacts

Co-Chair(s): M. C. Ozturk and M. Bauer
TimeAbs#Title and Authors
14:00   673   Silicides for 32nm and Beyond P. R. Besser (Advanced Micro Devices), C. Murray and C. Lavoie (IBM TJ Watson Research Center)
14:30   674   Material and Integration Issues for Rare Earth Silicides as Gate and Diffusion Contacts in Advanced CMOS Technologies C. P. D'Emic (IBM- T.J. Watson Research Center), K. Ohuchi (Toshiba America Electronic Components, NY), C. Murray, C. Lavoie (IBM TJ Watson Research Center), C. Scerbo, R. Carruthers (IBM- T.J. Watson Research Center, NY), P. R. Besser (Advanced Micro Devices) and B. Yang (Advanced Micro Devices, Inc., Yorktown Hgts., NY)
14:50   675   Ni(Pt)Si Thermal Stability Improvement By Carbon Implantation S. Mertens, T. Y. Hoffmann, C. Vrancken (Imec), S. Jakschik (Qimonda), O. Richard, H. Bender, W. Vandervorst, P. Absil and A. Lauwers (Imec)
15:10   676   Multi-Wavelength Raman and HRTEM Study of Ni/Si Interface after NiSi Formation at Low Temperatures using Various Heating Methods T. Sasaki, H. Minami, H. Harima, T. Isshiki, M. Yoshimoto (Kyoto Institute of Technology) and W. Yoo (WaferMasters, Inc.)
15:30   677   Effects of B or Al Interface Layers on Thermal Stability of Ni Silicide on Si K. Tsutsui, T. Shiozawa, K. Nagahiro, Y. Ohishi, K. Kakushima, P. Ahmet (Tokyo Institute of Technology), N. Urushihara, M. Suzuki (ULVAC PHI Inc.) and H. Iwai (Tokyo Institute of Technology)
15:50 Intermission (20 Minutes)
 

Novel Processes for Advanced Memory Technologies

Co-Chair(s): P. Timans and P. Besser
TimeAbs#Title and Authors
16:10   678   Memory Technologies for Sub-40nm: Materials, Processes, and Structures D. Ha and K. Kim (Samsung Electronics)
16:40   679   High Growth Rate SiO2 by Atomic Layer Deposition R. Matero, S. Haukka and M. Tuominen (ASM Microchemistry Ltd.)
17:00   680   Novel Batch Titanium Nitride CVD Process for Advanced Metal Electrodes P. M. Zagwijn, W. Verweij, D. Pierreux, N. Adjeroud, R. Bankras, E. Oosterlaken, G. Snijders (ASM International N.V.), M. Van den Hout (TU Delft), P. Fischer, R. Wilhelm and M. Knapp (ASM International N.V.)
17:20   681   Embedding of Nanocrystalline Ruthenium in ZrHfO High-k Film for Nonvolatile Memories C. Lin and Y. Kuo (Texas A&M University)