221st ECS Meeting - Seattle, Washington

May 6 - May 10, 2012

PROGRAM INFORMATION

 

E5 - Silicon Compatible Materials, Processes and Technologies for Advanced Integrated Circuits and Emerging Applications 2

 

Monday, May 7, 2012

Room 602, Level 6, Washington State Convention Center

Plenary

Co-Chairs: F. Roozeboom
TimeProgr#Title and Authors
08:35 Introductory Remarks (5 Minutes)
08:40   857   In Quest of a Fast, Low-Voltage Digital Switch T. N. Theis (IBM Research)
 

Strain Engineering/Contacts/Doping

Co-Chairs: P. Timans and S. Zhang
TimeProgr#Title and Authors
10:00   858   Ultrathin Ni1-xPtx Films as Electrical Contact in CMOS Devices S. Zhang (Uppsala University)
10:40   859   Characterization of Strain-Engineered Si:C Epitaxial Layers on Si Substrates W. Yoo, T. Ishigaki, T. Ueda, J. Kajiwara, K. Kang (WaferMasters, Inc.), P. Hung, K. Ang, and B. Min (SEMATECH)
11:00   860   Tensile Strained Si Seed Produced by Ion Implantation Technique L. Liu, Z. Xue, J. Bian, H. T. Jiang, X. Wei, Z. Di, and M. Zhang (Chinese Academy of Sciences)
11:20   861   Ultra Low-Temperature Epitaxial Growth of Strained Si Directly on Si Substrates D. Shahrjerdi, B. Hekmatshoar, S. W. Bedell, J. A. Ott, and M. Hopstaken (IBM T.J. Watson Research Center)
11:40   862   Pattern Dependency of Pure-Boron-Layer Chemical-Vapor Depositions V. Mohammadi, W. De Boer, T. L. Scholtes, and L. K. Nanver (Delft University of Technology)
 
TimeProgr#Title and Authors
13:40   863   The Enhancement of Etch Rate of Silicon by Heavy Doping of Phosphorus and Arsenic Atoms During Cyclic Selective Epitaxial Growth of Silicon K. Lee, Y. Kang, H. An, S. Jeong, J. Han, B. Kim, S. Nam, H. Kang, H. Jeong, C. Chung (Samsung Electronics Co. Ltd.), H. Park, and B. Choi (Sungkyunkwan University)
14:00   864   P-type Doping of Silicon Suitable for Structures with High Aspect Ratios by Using a Dopant Source of Boron Oxide Grown by Atomic Layer Deposition B. Kalkofen, V. Mothukuru (University of Magdeburg), M. Lisker (IHP), and E. P. Burte (University of Magdeburg)
14:20   865   Gas Source Depletion Study of High-Order Silanes of Silicon-Based Epitaxial Layers Grown with RPCVD and Low Temperatures K. H. Chung, P. Brabant, M. Shinriki (Matheson), H. He (IBM), D. K. Sadana (IBM T.J. Watson Research Center), S. Hasaka, and T. Francis (Matheson)
 

MEMS/NEMS

Co-Chairs: E. Gousev and A. Lal
TimeProgr#Title and Authors
15:00   866   From MEMS-CMOS towards Heterogeneous Integration over Scale H. Fujita, H. Toshiyoshi, and T. Ishida (The University of Tokyo)
15:40   867   Scaled Micro-Relay Structure with Low Strain Gradient for Reduced Operating Voltage I. Chen, L. Hutin (University of California, Berkeley), C. Park, R. Lee (SEMATECH, Inc.), R. Nathanael, J. Yaung (University of California, Berkeley), J. Jeon (Rutgers University), and T. King Liu (University of California, Berkeley)
16:00   868   Applications of Nanowire Enabled Micro Opto-Thermal Actuation A. Lal (Cornell University)
 

Tuesday, May 8, 2012

Room 602, Level 6, Washington State Convention Center

Bonding and 3D Integration

Co-Chairs: W. Lerch and D. L. Kwong
TimeProgr#Title and Authors
08:20   869   Advances in Materials and Processes for 3D-TSV Integration J. J. Lu (Rensselaer Polytechnic Institute)
09:00   870   Ge/Si p-n Diode Fabricated by Direct Wafer Bonding and Layer Exfoliation F. Gity, K. Byun, K. Lee, K. Cherkaoui, J. M. Hayes, A. P. Morrison, C. Colinge, and B. Corbett (University College Cork)
09:20   871   Wet-Chemical Silicon Wafer Thinning Process for High Chip Strength K. Yoshikawa (Tohoku University), T. Miyazaki (PRE-TECH AT CO., LTD), N. Watanabe, and M. Aoyagi (National Institute of Advanced Industrial Science and Technology)
 
TimeProgr#Title and Authors
10:00   872   New 3D LSIs Using Si Compatible Materials, Processes and Technologies M. Koyanagi, K. Lee, T. Fukushima, and T. Tanaka (Tohoku University)
10:40   873   Scaling Requires Continuous Innovation in Thermal Processing: Low-Temperature Plasma Oxidation W. Lerch, W. Kegel (Centrotherm Thermal Solutions GmbH & Co. KG), J. Niess, A. Gschwandtner (HQ-Dielectrics GmbH), and J. Gelpey (Centrotherm Thermal Solutions GmbH & Co. KG)
11:20   874   Heterogeneous Chip Integration into Silicon Templates by Through-Wafer Copper Electroplating C. D. Meyer, S. S. Bedair, S. M. Trocchia, M. A. Mirabelli, W. L. Benard, and T. G. Ivanov (U.S. Army Research Laboratory)
 

Gate Stack and Alternate Channels

Co-Chairs: V. Narayanan and R. Hill
TimeProgr#Title and Authors
13:30   875   Integration Challenges of III-V Materials in Advanced CMOS Logic R. J. Hill, W. Loh, J. Huang, T. Kim (SEMATECH), R. Lee (SEMATECH, Inc.), J. Oh, C. Hobbs, P. D. Kirsch, and R. Jammy (SEMATECH)
14:10   876   Enhancement in Electron Mobility at the Interface between Gd2O3(100) and n-type Si(100) W. Sitaputra and R. Tsu (University of North Carolina at Charlotte)
14:30   877   Heterepitaxial Growth of High Quality Germanium Layer on Si(001) in RPCVD for GOI Fabrication J. Bian, Z. Xue, D. Chen, Z. Di, and M. Zhang (Chinese Academy of Sciences)
14:50 Glen Wilk (ASM) Oral Presentation (40 Minutes)
 

FINFET/ETSOI/Nanowires

Co-Chairs: K. Kakushima and M. Masahara
TimeProgr#Title and Authors
15:50   878   Ultra-thin SOI/BOX Layers and Next Generations Planar Fully Depleted Substrates W. Schwarzenbach, V. Barec, X. Cauchy, N. Daval, S. Kerdiles, F. Boedt, O. Bonnin, B. Nguyen, and C. Maleville (SOITEC)
16:10   879   On-Current Variability Sources of FinFETs: Analysis and Perspective for 14nm-Lg Technology T. Matsukawa, Y. Liu, K. Endo, S. O'uchi, and M. Masahara (AIST)
16:50   880   Dynamical Observation of Epitaxial Growth of Copper Silicide/Silicon Nanowire Heterostructures C. Chiu, C. Huang, J. Chen, Y. Huang, and W. Wu (National Chiao Tung University)
 

Ballroom 6E, Level 6, Washington State Convention Center

Poster Session

Co-Chairs:
TimeProgr#Title and Authors
o   881   Nanocrystalline MoOx Embedded ZrHfO High-k Memories X. Liu, C. Yang, Y. Kuo (Texas A&M University), and T. Yuan (Ohio University)
o   882   Characterization of Grobal and Local Wafer Shape Change along Through Silicon Via Process Steps C. Lee, S. Jie, S. Park, H. Yoo, I. Han (Hynix Semiconductor Inc.), and W. Yoo (WaferMasters, Inc.)
o   883   The Effect of Plasma Treatment on Reducing Electroforming Voltage of Silicon Oxide RRAM F. Xue, Y. Chen, Y. Wang, F. Zhou (The University of Texas at Austin), B. Fowler (PrivaTran, LLC), and J. Lee (The University of Texas at Austin)
o   884   Development of High Selectivity Phosphoric Acid and Its Application to Flash STI Pattern S. Cho, Y. Lee, J. Han, H. Park, H. Kim, K. Hong, S. Park, and H. Kang (Hynix Semiconductor Inc.)
o   885   Electrical Improvement of MIS Capacitor with HfAlOx Gate Dielectrics Treated by Dual Plasma Treatment K. Chang (National Chaio Tung University), T. Chang, P. Chang, B. Huang (National Chiao Tung University), C. Wu (Chung Hua University), and I. Deng (Technology and Science Institute of Northern Taiwan)
o   886   Electrical and Reliability Characterization of Ti/TiN Thin Film Resistor Y. Cheng (National Chi-Nan University), B. Wei, and F. Lu (National Chung Hsing University)
o   887   The Bipolar Resistance Switching Behavior with a Pt/CoSiOX/TiN Structure of Nonvolatile Memory Device Y. Syu, T. Chang (National Sun Yat-Sen University), G. Chang (National Chiao Tung University), J. Lou, T. Tsai (National Sun Yat-Sen University), and Y. Tai (National Chiao Tung University)
o   888   Band Gap and Band Offset with Silicon of Amorphous High-k LaGdO3 Thin Films S. P. Pavunny, R. Thomas, and R. S. Katiyar (University of Puerto Rico)
o   889   Bipolar Resistive Switching Characteristics Using Al/Cu/GeOx/W Memristors S. Maikap and S. Rahaman (Chang Gung University)