Engineers have created a high-frequency electronic chip potentially capable of transmitting tens of gigabits of data per second, much faster than the fastest internet available today.

Omeed Momeni, an assistant professor of electrical and computer engineering at University of California, Davis, and doctoral student Hossein Jalili designed the chip using a phased array antenna system. Phased array systems funnel the energy from multiple sources into a single beam that can be narrowly steered and directed to a specific location.

“Phased arrays are pretty difficult to create, especially at higher frequencies,” Momeni says. “We are the first to achieve this much bandwidth at this frequency.”

The chip prototyped by Momeni and Jalili successfully operates at 370 GHz with 52 GHz of bandwidth. For comparison, FM radio waves broadcast between 87.5 and 108 MHz; 4G and LTE cellular networks generally function between 800 MHz and 2.6 GHz with up to 20 MHz of bandwidth.

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The future of technology

Image: Tau Zero/Flickr

The iconic Moore’s law has guided Silicon Valley and the technology industry at large for over 50 years. Moore’s prediction that the number of transistors on a chip would double every two years (which he first articulated at an ECS meeting in 1964) bolstered businesses and the economy, as well as took society away from the giant mainframes of the 1960s to today’s era of portable electronics.

But research has begun to plateau and keeping up with the pace of Moore’s law has proven to be extremely difficult. Now, many tech-based industries find themselves in a vulnerable position, wondering how far we can push technology.

Better materials, better chips

In an effort to continue Moore’s law and produce the next generation of electronic devices, researchers have begun looking to new materials and potentially even new designs to create smaller, cheaper, and faster chips.

“People keep saying of other semiconductors, ‘This will be the material for the next generation of devices,’” says Fan Ren, professor at the University of Florida and technical editor of the ECS Journal of Solid State Science and Technology. “However, it hasn’t really changed. Silicon is still dominating.”

Silicon has facilitated the growth predicted by Moore’s law for the past decades, but it is now becoming much more difficult to continue that path.

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The iconic Moore’s law has predicted the technological growth of the chip industry for more than 50 years. When ECS member and co-founder of Intel Gordon Moore proposed the law, he stated that the number of transistors on a chip would double every two years. So far, he’s been correct.

But researchers have started hitting an apex that makes keeping the pace of Moore’s law extremely difficult. It has become harder in recent years to make transistors smaller while simultaneously increasing the processing power of chips, making it almost impossible to continue Moore’s law’s projected growth.

However, researchers from MIT have developed a long-awaited tool that may be able to keep driving that progress.

(READ: “Moore’s Law and the Future of Solid-State Electronics“)

The new technology that hopes to keep Moore’s law going at its current pace is called extreme-ultraviolet (EUV) lithography. Industry leaders say it could be used in high-volume chip manufacturing as early as 2018, allowing continued growth in the semiconductor industry, with advancements in our mobile phones, wearable electronics, and many other gadgets.

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Since the development of the transistor in 1947, the semiconductor industry has been working to rapidly and continuously improve performance and processing speeds of computer chips. Following Gordon Moore’s iconic law—stating that transistor density would double every two years—the semiconducting silicon chip has propelled technology through a wave of electronic transformation.

Next Electronics Revolution

But all good things must come to an end. The process of packing silicon transistors onto computer chips is reaching its physical limits. However, IBM researchers state that they’ve made a “major engineering breakthrough” that provides a viable alternative to silicon transistors.

The team from IBM proposes using carbon nanotube transistors as an alternative, which have promising electrical and thermal properties. In theory, carbon nanotube transistors could be much faster and more energy efficient than currently used transistors. Nanotube transistors have never been utilized in the past due to major manufacturing challenges that prevented their wide-spread commercialization. However, the IBM researchers are combating this issue by combining the nanotubes with metal contacts to deliver the electrical current.

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In recent years, the semiconductor industry has struggled to keep up with the pace of the legendary Moore’s Law. With the current 14-nanometer generation of chips, researchers have begun to question if it will remain possible to double transistor density every two and a half years. However, IBM is now pushing away the doubt with the development of their new chip.

The new ultra-dense chip hosts seven-nanometer transistors, which yields about four times the capacity of our current computer chip. Like many other researchers in the field, IBM decided to move away for the traditional and expensive pure silicon toward a silicon-germanium hybrid material to produce the new chip.

The success of the high-capacity chip relies on the utilization of this new material. The use of silicon-germanium has made it possible for faster transistor switching and lower power requirements. And did we mention how impossibly small these transistors are?

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According to new research, black phosphorus may have the potential to outpace silicon.
Image: McGill University

We’re one step closer to atomic layer transistors due to recent research by a team of McGill University and Université de Montréal researchers. The new findings are the result of multidisciplinary work that yielded evidence that the material black phosphorus may make it possible to pack more transistors on a chip.

Researchers from McGill University joined with ECS’s Richard Martel in the Université de Montréal’s Department of Chemistry to examine if black phosphorus could tackle the prominent issue in the electronics field of designing energy-efficient transistors.

Similar to graphite, black phosphorus can be separate easily into single atomic layers to allow for thin transistors. When researchers are able to produce thinner transistors, they are also more efficient.

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When an electrical current is delivered to one of the chip’s tiny reservoirs, a single does of therapeutics releases into the body.
Image: MIT/Microchips Biotech

After extensive research, MIT engineers are on their way to commercializing microchips that release therapeutics inside of the body.

The implantable microchip-based device has the potential to outpace injections and conventional pills, changing the landscape of health care and treatment as we know it.

A startup stemming from MIT, Microchips Biotech, developed this technology and has partnered with Teva Pharmaceutical to get these chips into the market. Teva Pharmaceutical is a giant in the industry and the world’s largest producer of generic drugs.

This from MIT:

The microchips consist of hundreds of pinhead-sized reservoirs, each capped with a metal membrane, that store tiny doses of therapeutics or chemicals. An electric current delivered by the device removes the membrane, releasing a single dose. The device can be programmed wirelessly to release individual doses for up to 16 years to treat, for example, diabetes, cancer, multiple sclerosis, and osteoporosis.

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The high-performance 3D microbattery is suitable for large-scale on-chip integration.
Image: Engineering at Illinois

Engineers from the University of Illinois at Urbana-Champaign’s College of Engineering have developed a high-performance 3D microbattery applicable for large-scale on-chip integration with microelectronic devices.

“This 3D microbattery has exceptional performance and scalability, and we think it will be of importance for many applications,” said Paul Braun, professor of materials science and engineering at Illinois.

“Micro-scale devices typically utilize power supplied off-chip because of difficulties in miniaturizing energy storage technologies. A miniaturized high-energy and high-power on-chip battery would be highly desirable for applications including autonomous microscale actuators, distributed wireless sensors and transmitters, monitors, and portable and implantable medical devices.”

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Silicon is the common material used in solar cells and computer chips, but gallium arsenide is an alternative material with many advantages.
Image: YouTube/Stanford University

When we think of chips and solar cells, we think of silicon. However, silicon isn’t the only chip-making material out there.

Researchers from Stanford University are turning their attention away from silicon and are looking toward gallium arsenide to make faster chips and more efficient solar cells.

Gallium arsenide is a semiconductor material with extraordinary properties. Electrons can travel six times faster in gallium arsenide than in silicon, allowing for faster operation of transistors. Unfortunately, cost effectiveness is not one of gallium arsenide’s alluring properties—which has caused researchers to opt for the much cheaper and less effective silicon material.

One single wafer of gallium arsenide could cost up to $5,000, whereas the same size wafer of silicon costs only $5.

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Stanford engineers have created a four-layer prototype high-rise chip. The bottom and top layers are transistors, which are sandwiched between two layers of memory.
Credit: Max Shulaker, Stanford

Cheaper, smaller, and faster – those are the three words we’re constantly hearing when it comes to innovation and development in electronics. Now, Stanford University engineers are adding a fourth word to that mantra – taller.

The Stanford team is about to reveal how to build a high-rise chip that could vault the performance of the single-story logic and memory chips on today’s circuit cards – thereby preventing the wires connecting logic and memory from jamming.

This from Stanford University:

The Stanford approach would end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip. Many thousands of nanoscale electronic “elevators” would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.

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