High-Density Storage, 100 Times Less Energy

Tired of your electronics running out of memory? Rice University’s James Tour and his group of researchers have developed a solid state memory technology that allows for high-density storage while requiring 100 times less energy than traditional designs to operate.

The memory technology has been developed via tantalum oxide, a common insulator in electronics.

This from Futurity:

The discovery by the Rice University lab of chemist James Tour could allow for crossbar array memories that store up to 162 gigabits, much higher than other oxide-based memory systems under investigation by scientists. (Eight bits equal one byte; a 162-gigabit unit would store about 20 gigabytes of information.)

Read the full release here.

James Tour—a past ECS lecturer and pioneer in molecular electronics— and his group at Rice University’s Smalley Institute of Nanoscale Science & Technology are constantly demonstrating the interdisciplinary nature of nano science, and this is no exception. From the development of flexible supercapacitors to using cobalt films for clean fuel production, Tour and his lab are exploring many practical applications where chemistry and nano science intersect.


Layers of Logic Produce Skyscraper Chips

Stanford engineers have created a four-layer prototype high-rise chip. The bottom and top layers are transistors, which are sandwiched between two layers of memory.
Credit: Max Shulaker, Stanford

Cheaper, smaller, and faster – those are the three words we’re constantly hearing when it comes to innovation and development in electronics. Now, Stanford University engineers are adding a fourth word to that mantra – taller.

The Stanford team is about to reveal how to build a high-rise chip that could vault the performance of the single-story logic and memory chips on today’s circuit cards – thereby preventing the wires connecting logic and memory from jamming.

This from Stanford University:

The Stanford approach would end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip. Many thousands of nanoscale electronic “elevators” would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.