204th Meeting of The Electrochemical Society, Co-sponsored in Part by the Electronics Division of The American Ceramic Society
October 12-October 16, 2003
PROGRAM INFORMATION
G1 - Copper Interconnections, Low-k Inter-Level Dielectrics, and New Contact Metallurgies/Structures
Dielectric Science and Technology/Electronics/Electrodeposition
Monday, October 13, 2003
Cloister North, Lobby Level
Barrier Films
Co-Chairs: G.S. Mathad and V. Bakshi
| Time | Abs# | Title |
|---|
| 10:00 | 590 |
The Proposal of All-wet Fabrication Process for ULSI Interconnects Technologies - Application of Electroless NiB Deposition to Capping and Barrier Layers - - T. Yokoshima, M. Yoshino, and T. Osaka (Waseda University) |
| 10:20 | 591 |
Resistivity and Diffusion Barrier Properties of ZrN in Cu/ZrN/Si Systems - C.-S. Chen, C.-P. Liu, and H.-G. Yang (S/C Technology Consulting) |
| 10:40 | 592 |
Characterization of Electroless Plated CoWB Barrier Films - V. Mathew, R. Chatterjee, S. Garcia, L. Svedberg, Z.-X. Jiang, R. Gregory, K.-H. Lie, and K. Yu (Motorola Inc.) |
| 11:00 | 593 |
Effect of Crystallinity of Ta2N on Diffusion Barrier Properties - H.-C. Chung and C.-P. Liu (National Cheng Kung University) |
| 11:20 | 594 |
Electrical and Physical Characterization of Cobalt Silicide Growth with Alternative Cap Layers - M. Vulpio, D. Fazio, M. Bileci, D. Mello, and C. Gerardi (STMicroelectronics) |
| 11:40 | 595 |
Ruthenium-based Copper Diffusion Barrier :Studied by Electrochemistry, SIMS Depth Profiling and Sheet Resistance Measurements - O. Chyan, R. Chan, T. Arunagiri, R. Wallace (University of North Texas), T. Hurd (Texas Instruments), and M.J. Kim (University of North Texas) |
Copper Deposition
Co-Chairs: C. Reidsema Simpson and M. Koyanagi
| Time | Abs# | Title |
|---|
| 2:00 | 596 |
Relation of Contact Resistance Reduction and Process Parameters of Bonded Copper Interconnects in Three-Dimensional Integration Technology - K.-N. Chen, A. Fan, C.S. Tan, and R. Reif (Massachusetts Institute of Technology) |
| 2:20 | 597 |
Ultra-Thin Tungsten CVD Nucleation Layer for Sub 100nm Contact Applications - J. Gupta, J. Sudijono, L.C. Hsia (Chartered Semiconductor Manufacturing Ltd.), and S. Singh (Applied Materials South East Asia Pte Ltd) |
| 2:40 | 598 |
3-Dimensional Chip Stacking for High-Density Electronic Packaging - K. Takahashi, K. Tanida, M. Umemoto, K. Kojima (ASET - Tsukuba Research Center), M. Ishino, and M. Bonkohara (ASET - Headquarter Office) |
| 3:10 | 599 |
Three-Dimensional Integration Technology Using Novel Stacked Wafer Polishing (SWAP) Method - M. Koyanagi, T. Nakamura, Y. Yamada, J. Shim, and H. Kurino (Tohoku University) |
| 3:40 | |
Twenty-Minute Intermission |
| 4:00 | 600 |
Copper Electrodeposition of High-Aspect-Ratio Vias for Three Dimensional Packaging - K. Kondo, T. Yonezawa (Okayama University), M. Tomisaka, H. Yonemura, M. hoshino, and K. Takahashi (ASET) |
| 4:30 | 601 |
Copper Electroplating Process with Improved Stability, Conductivity, and Total Cost of Ownership - R. Preisser, T. Dretschkow (Atotech Deutschland), and H. Fuerhaupter (Atotech USA) |
| 4:50 | 602 |
Electroplating of Copper-Tin Alloys - R. Chebiam, C.-C. Cheng, H. Simka, A. Budrevich, and V. Dubin (INTEL Corporation) |
| 5:10 | 603 |
Interactions between the Conditions of Copper Electrodeposition and the Density of Hillocks - S. Petitdidier, M. Grégoire, S. Segaud (ST Microelectronics), S. Courtas (Philips Semiconductor), M. Juhel (ST Microelectronics), J.-P. Jacquemin (Philips Semiconductor), and L. Dumas (ST Microelectronics) |
Tuesday, October 14, 2003
Copper Deposition and Low-k Inter-level Dielectrics
Co-Chairs: K. Kondo and J. Chapple-Sokol
| Time | Abs# | Title |
|---|
| 8:20 | 604 |
Detection of Accelerator Breakdown Products in Copper Plating Baths - M. Pavlov, E. Shalyt, P. Bratin, and D.M. Tench (ECI Technology, Inc.) |
| 8:40 | 605 |
Copper Nucleation on Platinum in the Presence of Additives in Acid-Copper Solution - T. Baum, J. Han, M. King, and M. Stawasz (ATMI) |
| 9:00 | 606 |
Influence of the Anode in the Damascene Process Investigated by EIS - C. Gabrielli, P. Mocoteguy, H. Perrot (UPR 15 du CNRS), A. Zdunek, D. Nieto-Sanz (Air Liquide), and M. Clech (ALTIS Semiconductor) |
| 9:20 | 607 |
Investigation of Bath Aging in the Damascene Process by EIS - C. Gabrielli, P. Mocoteguy, H. Perrot (UPR 15 CNRS LISE), A. Zdunek, D. Nieto-Sanz (Air Liquide), and M. Clech (ALTIS Semiconductor) |
| 9:40 | |
Twenty-Minute Intermission |
| 10:00 | 608 |
Electrical and Mechanical Properties of Nitrogen and Fluorine Incorporated Organosilicate Glass Prepared by Plasma Enhanced Chemical Vapor Deposition - S.-K. Jangjian, C.-P. Liu (National Cheng Kung University), Y.-L. Wang (Taiwan Semiconductor Manufacturing Company), and W.-S. Hwang (National Cheng Kung University) |
| 10:20 | 609 |
Development of Spin-on Dielectric (SiLK TM) Etch Process for 0.13 Micrometers Cu-Low k Interconnects Technology - B.R. Murthy (Institute of Microelectronics) |
| 10:40 | 610 |
Plasma Etching of Porous Dielectric Substrates - M. Bloomfield, Y.H. Im, and T. Cale (Rensselaer Polytechnic Institute) |
| 11:00 | 611 |
Reducing Plasma-Induced Damage for 65 nm Technology Node Cu/Low-k Interconnects - L. Li, T. Tanaka, D. Sugiarto, T. Huang, L.-Q. Xia, and P. Lee (Applied Materials Inc.) |
| 11:20 | 612 |
Alternative Approaches to Eliminate the Photoresist Poisoning Issue in Low-k BEOL Integration - R. Hung, M. Naik, S. Parikh, H. Du, H. Dai, X. Xu, N. Vasquez, P. Xu, C. Bencher, K. Nelson, M. Amarcost, and G. Dixit (Applied Materials) |
| 11:40 | 613 |
Mechanisms of Vapor Cleaning of Copper Surface Using Organic Acids - T. Yagishita, K. Ishikawa, and M. Nakamura (Association of Super-Advanced Electronics Technologies) |
Low-k Inter-level Dielectrics and CMP
Co-Chairs: H.S. Rathore and T. Cale
| Time | Abs# | Title |
|---|
| 2:00 | 614 |
Characterization of Plasma Strip Processes on OSG Low-k Dielectric Films - S. Li, I.J. Kalinvoski, J. Su, and G.W. Hills (Novellus Systems, Inc.) |
| 2:20 | 615 |
Strip Process Optimization for Porous ULK Films - I.J. Kalinovski, S. Li, A. Marfoure, J. Su, G. Hills (Novellus Systems, Inc.), C. Bourlot, O. Louveau, and D. Louis (LETI) |
| 2:40 | 616 |
The Pore Structure and Property of a Spin-on Porous Low k Dielectric - Y. Liu (Intel Assignee at International Sematech), W.-L. Wu (NIST), B. Foran (Intel Assignee at International Sematech), D. Gidley (University of Michigan), H. Shirataki, and H. Hanahata (Asahi Kasei Co.) |
| 3:00 | 617 |
Single Wafer Wet Cleans Development for Cu/Low-k Technologies: Efforts on SiLK - L. Archer, S.-A. Henry, and Z. Hatcher (SEZ America) |
| 3:20 | |
Twenty-Minute Intermission |
| 3:40 | 618 |
Reliability Characterization of Organic Ultra Low K Film Using Ramp Voltage Breakdown - B.R. Murthy and A. Krishnamoorthy (Institute of Microelectronics) |
| 4:00 | 619 |
Process-induced Voiding in Copper Interconnect Metallization - P. Lindgren, K. Downes, S. Cole, W. Murphy, E. Cooney, M. Goldstein, and J. Chapple-Sokol (IBM Microelectronics Division) |
| 4:20 | 620 |
Polishing Behavior of Metal and Interlayer Dielectric (ILD) Materials with Different Slurries - A. Sikder, P. Zantye, and A. Kumar (University of South Florida) |
| 4:40 | 621 |
Planarization of Copper Layer for Damascene Interconnection by Electrochemical Polishing in Alkali-based Solution - G.-S. Park, Y.-J. Oh, and C.-H. Chung (Sungkyunkwan University) |
| 5:00 | 622 |
Characterization of a Colloidal Silica Slurry for 0.13um and 0.18um Devices in a Copper CMP Process - J. Cadenhead, G. Huffman, D. Lewis, A. Pamatat, J. Verizzo (Motorola, Inc. Semiconductor Products Sector), and S. Usmani (DuPont Air Products Nanomaterials) |
Exhibit Hall, Ground Level
Technical Exhibit and Poster Session, 7:00 - 9:00 PM
Co-Chairs: G.S. Mathad and H.S. Rathore
| Time | Abs# | Title |
|---|
| o | 623 |
Evaluation of Low-k Porous Silica Film Incorporated with Ethylene Groups - Y. Uchida and M. Oikawa (Teikyo University of Science and Technology) |
| o | 624 |
A Novel Approach for Dual Damascene Trench Etch for 90 nm Low-k Interconnect with No Middle Etch Stop Layer - T.Q. Chen (Chartered Semiconductor Manufacturing Ltd.), R.K. Jaiswal (Applied Materials South East Asia Pte. Ltd.), P. Yelehanka (Chartered Semiconductor Manufacturing Ltd.), A. Jain, I. Sim (Applied Materials South East Asia Pte. Ltd.), and W.P. Liu (Chartered Semiconductor Manufacturing Ltd.) |
| o | 625 |
New Additives for Superconformal Electroplating of Ag Thin Film for ULSI - E.J. Ahn and J.J. Kim (Seoul National University) |
| o | 626 |
Electrodeposition of Copper on n-type GaAs for Schottky Barriers - L. Su (Virginia Commonwealth University) |
| o | 627 |
An in-situ FTIR Study on Palladium Displacement Reaction for Autocatalytic Electroless Copper Deposition - Y.-J. Oh and C.-H. Chung (Sungkyunkwan University) |
| o | 628 |
The Influence of 2,2'-Dipyridyl on Non-formaldehyde Electroless Copper Plating - J. Li, H. Hayden, and P. Kohl (Georgia Institute of Technology) |
| o | 629 |
The Role of Chloride Ion in Copper Electrodeposition from Acidic Baths Containing Cl, PEG, and SPS - M. Tan and J.N. Harb (Brigham Young University) |
| o | 630 |
Investigation of the Mechanism of Electroless Deposition of Ni-P Alloy, Its Adhesion and Ductility - T. Khoperia, L. Maisuradze, S. Esaiashvili, T. Petriashvili, and N. Khoperia (E. Androonikashvili Insitute of Physics) |
| o | 631 |
Three-Dimensional Simulation of Superconformal Copper Deposition Based on the Curvature-Enhanced Accelerator Coverage Mechanism - E. Bar, J. Lorenz, and H. Ryssel (Fraunhofer Institute of Integrated Systems and Device Technology) |
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