201st Meeting - Philadelphia, PA

May 12-17, 2002

PROGRAM INFORMATION

N1 - Ninth International Symposium On Silicon Materials Science and Technology

Electronics

Monday, May 13, 2002

Salon F, Level 5

Plenary Session

Co-Chairs: H.R. Huff and L. Fabry

TimeAbs#Title
10:00 Introductory Remarks by H.R. Huff -
10:05552 The 2002 International Technology Roadmap for Semiconductors (ITRS) - P. Gargini (Intel Corp.)
10:45553 Realizing the Future for the Semiconductor Industry - Meeting the Challenges of Process, Design, and Business - C.M. Melliar-Smith and C.R. Helms (International SEMATECH)
11:25554 Establishment of a Device Process Platform for Realizing a Leading-Edge System-on-a-Chip - A. Morino (Semiconductor Leading Edge Technologies, Inc.)

Plenary Session

Co-Chairs: L. Fabry and S. Kishino

TimeAbs#Title
2:00 Introductory Remarks by Fabry -
2:05555 IMEC's Research Programs and the ITRS Challenges - G.J. Declerck (IMEC)
2:45556 Foundry Technology in SOC ERA - S.Y. Chiang (Taiwan Semiconductor Manufacturing Company)
3:25557 MIRAI Project - M. Hirose (National Institute of Advanced Industrial Science and Technology)
4:05 Ten-Minute Intermission -

Plenary Session

Co-Chairs: S. Kishino and H.R. Huff

TimeAbs#Title
4:15 Introductory Reamrks by Kishino -
4:20558 China's Semiconductor Industry and the Global IC Environment - H. Tu (National Engineering Research Center for Semiconductor Materials)
5:00559 Ways of Cooperation in the Field of the Silicon Technology - M. Brillouet (CEA-LETI)
5:40560 Long-Term Productivity Mechanisms of the Semiconductor Industry - R. Goodall, D. Fandel, and H. Huff (International SEMATECH)

Tuesday, May 14, 2002

Silicon Materials 300 MM

Co-Chairs: W. Von Ammon and T. Shigematsu

TimeAbs#Title
8:00561 Control of Point Defects, Impurities, and Extended Defects in Si: The Original/Ongoing Silicon Nanoscale Defect Engineering - G. Rozgonyi (North Carolina State University)
8:30562 Super Silicon Initiative and Future Large Wafer Size Diameters - M. Kuramoto (Sumimoto Mitsubishi Silicon Corporation)
9:00563 300mm Substrate Requirements for Advanced DRAM Technolgies - H. Dietrich, C. Kupfer, and J. Martin (Infineon Technologies)
9:30 Twenty-Minute Intermission -

Silicon Materials 300 MM

Co-Chairs: T. Shigematsu and W. Von Ammon

TimeAbs#Title
9:50564 Growth of 300 mm Silicon Single Crystals in a 24i+/- Hot Zone - H. Tu, X. Dai, Z. Wu, G. Zhang, J. Wang, F. Fang, Q. Zhou, and Q. Xiao (National Engineering Research Center for Semiconductor Materials)
10:10565 Study on Geometry, Surface Damage and Rapid Thermal Annealing of 300 mm As-cut Silicon Wafers - G. Zhang, B. Liu, J. Zhao, W. Chen, J. Wang, Q. Zhou, and H. Tu (National Engineering Research Center for Semiconductor Materials)
10:30566 Argon-Annealed 300mm Wafer Complementing pp-Epitaxial Layers - T. Muller, W. Siebert, R. Wahlich, P. Krottenthaler, A. Ikari, K. Mebmann, R. Holzl, and W. von Ammon (Wacker Siltronic AG)

Silicon Materials Generic Issues

Co-Chairs: W. Von Ammon and T. Shigematsu

TimeAbs#Title
2:00567 Thermophysical Properties of Intrinsic Point Defects in Crystalline Silicon - T. Sinno (University of Pennsylvania)
2:30568 Impact of Silcon Bulk Defects on Deep Submicron Design-Rule DRAM Services - E. Dorneberger (Wacker Siltonic AG), D. Temmler (Infineon Technologies), and W. von Ammon (Wacker Siltonic AG)
2:50569 Fractional Contribution in Si Self-Diffusion: Dopant Concentration and Temperature Dependence on Si Self-Diffusion Mechanism - Y. Nakabayashi, H.I. Osman, K. Toyonaga, K. Yokota, S. Matsumoto (Keio University), J. Murota (Tohoku University), K. Wada (Massachusetts Inst. of Technology), and T. Abe (ShinEtsu Handootai)
3:10570 Effect of Vacancy Double Acceptor Level in Si Self-Diffusion Under Heavy Doping Condition - H.I. Osman, Y. Nakabayashi, T. Sakaguchi, K. Toyonaga (Keio University), J. Murota (Tohoku University), K. Wada (Massachusetts Inst. of Technology), T. Abe (ShinEtsu Handootai), and S. Matsumoto (Keio University)
3:30571 Wafers with Low LPD and Reduced Haze Prepared by Short Annealing Process - J.L. Vasat, A.D. Stefanescu, T. Torack (MEMC Electronic Materials, Inc.), and R. Orizio (MEMC Electronic Materials, Spa.)
3:50 Ten-Minute Intermission -

Silicon Materials Generic Issues

Co-Chairs: T. Shigematsu and W. Von Ammon

TimeAbs#Title
4:00572 Oxidation-Induced Stacking Faults in Nitrogen Doped Czochralski Silicon - D. Yang, J. Chu, X. Ma, L. Li, and D. Que (Zhejiang University)
4:20573 Impact of Nitrogen Doping in Silcon onto Gate Oxide Integrity - A. Huber, M. Kasper, J. Grabmeier, U. Lambert, W.V. Ammon, and R. Pech (Wacker Siltronic AG)
4:40574 Atomic Layer Doping of N in Si Epitaxial Growth on Si (100) and its Thermal Stability - J. Murota, Y.C. Jeong, M. Sakuraba, and T. Matsuura (Tohoku University)
5:00575 A Technique for Delineating Defects in Silicon - L. Mule'Stagno (MEMC Electronic Materials Inc.)
5:20576 Growth Technology for 200 mm Antimony Heavily Doped Silicon Single Crystals - Q. Zhou, F. Qin, J. Zhou, F. Fang, J. Wang, and H. Tu (National Engineering Research Center for Semiconductor Materials)
5:40577 Silicon Epitaxy and Particle Dynamics: A Theoretical and Experimental Study - S. Kommu (MEMC Electronic Materials, Inc.)

Process Modeling

Co-Chairs: H. Richter and P. Mertens

TimeAbs#Title
8:00578 Physical and Predictive Models of Ultra Thin Oxide Reliability in CMOS Devices and Circuits - J. Stathis (IBM Research Division)
8:30579 Low Voltage Gate Dielectric Reliability - B. Weir, M. Alam, and P. Silverman (Agere Systems)
9:00580 Electric Stress-Induced Degradation of Thin Oxide Layers and Its Impact on Device Reliability - R. Degraeve, B. Kaczer, P. Roussel, and G. Groeseneken (IMEC)
9:30 Sixty-Minute Audience Discussion -

Wednesday, May 15, 2002

Alternative Materials and IC Processing Technologies

Co-Chairs: H. Iwai and W. Maszara

TimeAbs#Title
8:30581 SOI Technology: The Future Will Not Scale Down - S. Cristoloveanu (IMEP, ENSERG)
9:00582 SiGeC Device Applications - H.J. Osten (IHP)
9:30 Ten-Minute Intermission -
9:40583 NiSi Salicide for Sub-100nm CMOS - Q. Xiang (Advanced Micro Devices, Inc.)
10:10584 Current and Future High-K Capacitor Technology for DRAM Applications - K. Hieda (Toshiba Corporation)
10:40585 Rare Earth Metal Oxides for High-K Gate Insulator - S. Ohmi, S. Akama, A. Kikuchi, I. Kashigwagi, C. Ohshima, J. Taguchi, H. Yamamoto, K. Sato, M. Takeda, H. Ishiwara, and H. Iwai (Tokyo Inst. of Technology)

Alternative Materials and IC Processing Technologies

Co-Chairs: W. Maszara and H. Iwai

TimeAbs#Title
2:00586 Electronic Structure of Non-crystalline High-k Transition-metal and Rare Earth Oxides and Their Silicate and Aluminate Alloys - Y. Zhang, G. Lucovsky, B. Rayner, G. Appel, and J. Whitten (NC State University)
2:20587 Interpretation of Non-linear Chemical Shifts in XAP/AES Features in Non-crystalline Zirconium Silicate Alloys: (ZrO2)x(SiO2)1-x - B. Rayner, D. Kang, and G. Lucovsky (North Carolina State University)
2:40588 Interface Reactions During Oxygen Plasma Assisted Chemical Vapor Deposition of Yttrium Oxide on Silicon - D. Niu, R. Ashcraft (North Carolina State University), S. Stemmer (Rice University), and G. Parsons (North Carolina State University)
3:00589 Study of Diffusivity and Electrical Properties of Zr and Hf in Silicon - O. Vyvenko, R. Sachdeva, A. Istratov, R. Armitage, E. Weber (University of California), P.N.K.(S. Deenapanray, C. Jagadish (Australian National University), Y. Gao (Applied Microanalysis Labs), and H. Huff (International Sematech)
3:20 Ten-Minute Intermission -

Process Modeling

Co-Chairs: P. Mertens and H. Richter

TimeAbs#Title
3:30590 Simulation of Crystal Pulling and Comparison to Experimental Analysis Cz-Process - G. Muller (University Erlangen), O. Grabner (Fraunhofer Inst. for Integrated Circuits), and D. Vizman (West University of Timisoara)
4:00591 Grown in Microdefect Distribution in Doped Silicon Crystals - G. Borionetti, D. Gambaro, M. Porrini, and V. Voronkov (MEMC Electronic Materials)
4:20592 Calculation of Size Distribution of Void Defect in Czochralski Silicon - M. Akastsuka, M. Okui, S. Umeno, and K. Sueoka (Sumimoto Metal Industries Ltd.)
4:40593 Modelling of Crystal Originated Particles and their Impact on Gate Oxide Integrity - T. Bearda, P. Mertens (Interuniversity Micro-Electronics Center), P. Woerlee, H. Wallinga (University of Twente), R. Schmolke (Wacker Siltronic AG), and M. Heyns (Interuniversity Micro-Electronics Center)
5:00594 Computer Simulation for Morphology , Size, and Density of Oxide Precipitates in Czochraiski Silicon - K. Sueoka, M. Akatsuka, M. Okui, and H. Katahama (Sumimoto Metal Industries, Ltd.)
5:20595 Simulation of the Point Detect Diffusion and Growth Condition for Defect-free Silicon Crystal - K. Nakamura, T. Saishoji, and J. Tomioka (Komatsu Electronic Metals Co., Ltd.)
5:40596 Modeling of SiGe Epitaxial Growth in a Wide Range of Growth Conditions - A. Segal, A. Sid'ko, S. Karpov (Soft Impact Ltd), and Y. Makarov (STR, Inc)

Thursday, May 16, 2002

Process Modeling

Co-Chairs: H. Richter and P. Mertens

TimeAbs#Title
8:00597 Unified Theory of Thermal Silicon Oxide Growth - M. Uematsu, H. Kageshima, and K. Shiraishi (NTT Basic Research Labs)
8:30598 Characterization of the Mechanical Stress Induced During silicidation in Sub-0.25UM Mos Technologies - A. Steegen (IBM Microelectronics)
9:00599 Gettering Efficiencies and Their Depence on Material Parameters and Thermal Processes: How Can This Be Modeled? - R. Hoelzl, M. Blietz, L. Fabry, and R. Schmolke (Wacker Siltronic AG)
9:30 Ten-Minute Intermission -
9:40600 Modeling of Competitive Gettering Between Devices and Gettering Sites - A. Istratov (University of California, Berkeley), W. Huber (Sumitomo Sitix Silicon), and E. Weber (University of California, Berkeley)
10:00601 Determination of Minimum Oxygen Precipitate Growth Conditions for Gettering of Copper and Nickel - M. Seacrist, M. Stinson, J. Libbert, R. Standley, and J. Binns (MEMC Electronic Materials, Inc.)
10:20602 Effective Intrinsic Gettering for 200mm and 300mm P/P- Wafers in a Low Thermal Budget 0.13um Advanced CMOS Logic Process - M. Binns, S. Bertolini (MEMC Electronic Materials Inc.,), R. Wise, D. Myers, and T. McKenna (Texas Instruments Incorporated)
10:40 Ten-Minute Intermission -

Process Modeling

Co-Chairs: P. Mertens and H. Richter

TimeAbs#Title
10:50603 Bulk Micro Defects of p/p- Epitaxial Silicon Wafers with Nitrogen Doped Substrates and Their Gettering Behavior - R. Schmolke, M. Blietz, R. Holzl, D. Menzel (Wacker Siltonic AG), and H. Bender (IMEC)
11:10604 First Principles Calculations for Nitrogen-Vacancy Related Defects in N-CZ Si - A. Karoui, F. Sahtout Karoui, G.A. Rozgonyi (North Carolina State University), M. M. Hourai, and K. K. Sueoka (Sumitomo Metal Industries, Ltd.)
11:30605 The Control of Boron Autodoping During Device Processing for P/P+ Epi-Wafers With No Back-Surface Oxide Seal - M. Binns, S. Kommu, M. Seacrist, R. Standley (MEMC Electronic Materials, Inc), R. Wise, D. Myers, D. Tisserand, and D. Doyle (Texas Instruments Incorporated)
11:50606 Impact of State-of-the-art Cz Substrates on the Current-Voltage Characteristics of Shallow p-n Junctions - A. Poyai, E. Simoen, C. Claeys (IMEC), A. Huber, D. Graf (Wacker Siltronic AG), and E. Gaubas (Vilnius University)

Process Integration

Co-Chairs: P. Tobin and S. Deleonibus

TimeAbs#Title
2:00607 Invention of Stacked Capacitor DRAM Cell - M. Koyanagi (Tohoku University)
2:30608 CMOS Technology Roadmap: Approaching Up-Hill Specials - T. Stotnicki and F. Bouef (STMicroelectronics)
3:00609 The High K Challenges in CMOS - E. Young (International SEMATECH)
3:30610 Integration Issues of Polysilicon with High k Dielectrics Deposited by Atomic Layer Chemical Vapor Deposition - W. Tsai, J. Chen (International Sematech), R. Carter, E. Cartier (IMEC), J. Kluth (International Sematech), O. Richard (IMEC), M. Claes (ASM International), Y.M. Lin (International Sematech), Y. Manabe, H. Nohira, T. Conard, M. Caymax (IMEC), E. Young (International Sematech), W. Vandervorst, S. Degendt, M. Heyns (IMEC), J.W. Maes (ASM International), C. Rittersma, and F. Roozeboom (Philips Research)
3:50 Ten-Minute Intermission -

Process Integration

Co-Chairs: S. Deleonibus and P. Tobin

TimeAbs#Title
4:00611 A New Junction Technology Based on Selective CVD of Sige for CMOS Technology Nodes Beyond 30 NM - M. Ozturk, N. Pesovic, J. Liu, H. Mo, I. Kang, and S. Gannavaram (North Carolina State University)
4:30612 Avoiding Furnace Slip in the Era of Shallow Trench Insulation - A.E. Stephens (MEMC Electronic Materials)
4:50613 Effective Intrinsic Gettering of Copper During a Sub-quarter Micron CMOS Process - K.-M. Bae, J.-R. Kim, Y.-K. Hong (MEMC Korea Co. Ltd.), S.-I. So, S.-C. Lee, S.-S. Kim, S.-W. Ha, C.-G. Koh, S.-H. Pyi (Hynix Semiconductor), and D.-M. Lee (MEMC Electronic Materials, Inc.)
5:10614 Damascene Metal Gate for 70 NM Cmos Process - B. Guilaumot (STM Microelectronics), F. Ducroquet (UMR), G. Guegan, C. Renard, B. Previtali (CEA), M. Rivoire, M.E. Nier (STM Microelectronics), S. Tedesco, T. Fargeot, H. Achard, and S. Deleonibus (CEA)
5:30615 Effect of Wafer Backside Clean Process on the ULSI Lithography - N. Balasubramanian, R. Moitreyee-Mukherjee, P. Lau. H. G., and F.P. Dow (Instite of Microelectronics)

Friday, May 17, 2002

Integrated Metrology and Diagnostics

Co-Chairs: A. Diebold and H. Koyama

TimeAbs#Title
8:00616 Characterization of SOI Wafers by Photoluminescence - M. Tajima and S. Ibuka (Institute of Space and Aeronautical Science)
8:30617 Electrical Characterization of SOI Wafers Scanning Probe Microscopy - T. Uchihashi, Y. Ishizuka, H. Yashida, and S. Kishino (Himeji Institute of Technology)
8:50618 Defect Management and Yield Enhancement for the Semiconductor Industry - M. Bennett (Texas Instruments)
9:20619 Integrated Metrology and Advanced Process Control in Semiconductor Manufacturing - A. Shanmugasundram, M. Sarfaty, A. Schwarm, and J. Paik (Applied Materials)
9:50620 Evaluation Technology for Time-Dependent Orgnic Contamination on Silicon Wafer Surfaces - H. Habuka (Yokohama National University), S. Ishiwari (Hitachi Plant Engineering & Construction Co., Ltd.), and H. Kato (Hitachi Ltd.)
10:10 Ten-Minute Intermission -

Integrated Metrology and Diagnostics

Co-Chairs: H. Koyama and A. Diebold

TimeAbs#Title
10:20621 Measurement of Nitrogen Concentration in CZ Silicon - N. Inoue, K. Shingu, and K. Matsumoto (Japan Electronics & Information Technology Association)
10:50622 Experimental Method to Determine an Acceptable Concentration of Iron Impurity in Hot Zone Structural Components - H. Sreedharamurthy, M. Seacrist, J. Holder, and M. Banan (MEMC Electronic Materials, Inc.)
11:10623 Effect of Oxide Thickness on Dielectric Breakdown Induced by Surface COP - K. Yamabe, Y. Shimada, M. Piao, T. Yamazaki, T. Otsuki, R. Takeda, Y. Ohta, S. Jimbo, and M. Watanabe (GOI Task Force SOI Wafer Committee)
11:30624 Microroughness Analysis of Silicon Wafers Using Ultraviolet Raman Microscopy - J. Wang, H. Tu, B. Liu, Q. Zhou, and W. Zhu (National Engineering Research Center for Semiconductor Materials)
11:50625 The Behaviour of Oxygen in Oxygenated N-Type High-Resistivity Float-Zone Silicon - E. Simoen, C. Claeys (IMEC), R. Job, A. Ulyashin, W. Fahrner (University Hagen), G. Tonelli (INFN), O. Degryse, and P. Clauws (University of Ghent)

Ultimate Silicon and End-of-Roadmap Devices

Co-Chairs: S. Hillenius and S. Ishihara

TimeAbs#Title
1:30626 50 nm Vertical Replacement-Gate (VRG) nMOSFETs with ALD HfO_2 Gate Dielectrics - J. Hergenrother, T. Nigam, G. Wilk, F. Klemens, D. Monroe, T. Sorsch, B. Busch, M. Green (Agere Systems), D. Muller, P. Voyles, J. Grazul (Bell Laboratories, Lucent Technologies), E.J. Shero, M.E. Givens, C. Pomarede, M. Mazanec, and C. Werkhoven (ASM America)
2:00627 Electrochemical Properties of Nanometer-Scale Mosfets - H. Kawaura and T. Sakamoto (NEC Corporation)
2:30628 Interband Tunneling-Based ULSI-Compatible Silicon Devices - A. Zaslavsky (Brown University), D. Mariolle, S. Deleonibus, D. Fraboulet (LETI), S. Luryi (SUNY at Stony Brook), J. Liu, C. Aydin (Brown University), M. Mastrapasqua, R.W. Johnson, and C.A. King (Agere Systems)
2:50 Ten-Minute Intermission -

Ultimate Silicon and End-of-Roadmap Devices

Co-Chairs: S. Ishihara and S. Hillenius

TimeAbs#Title
3:00629 Silicon Single-Electron Devices and Their Application to Logic Circuits - Y. Takahashi, Y. Ono, A. Fujiwara, and H. Inokawa (NTT Corporation)
3:30630 Single-electron and Nanoscopic Device Evolution - F. Kreupl (Infineon Technologies AG)
4:00631 Bottoms-up Approach in Si Technology Based on Surface Structure Design - T. Ogino, Y. Homma, Y. Kobayashi, H. Hibino, K. Prabhakaran, K. Sumitomo, H. Omi, D. Bottomley, A. Kaneko, and F. Ling (NTT Basic Research Labs)