203rd Meeting - Paris, France
April 27-May 2, 2003
PROGRAM INFORMATION
L1 - ULSI Process Integration III
Electronics/IEEE Electron Devices Society
Monday, April 28, 2003
Room 252A, Level 2, Le Palais des Congres
Co-Chairs: C.L. Claeys and H. Iwai
Co-Chairs: R. Singh and C. Osburn
| Time | Abs# | Title |
|---|
| 13:40 | 953 |
Current Status and Future Prospects in Mixed Signal SoC - A. Matsuzawa (Matsushita Electric Industrial Co., Ltd.) |
| 14:20 | 954 |
DRAM Technology for 100nm and Beyond - K.H. Kuesters (Infineon Technologies) |
| 14:45 | 955 |
Logic Based Embedded DRAM Technologies - C. Mallardeau (STMicroelectronics) |
| 15:10 | 956 |
Flash Memory Technology Evolution - R. Bez and E. Camerlenghi (STMicroelctronics) |
| 15:35 | 957 |
FeRAM Technology : Today and Future - I. Kunishima (Toshiba Corporation) |
| 16:10 | 958 |
Single-Wafer Technology in a 300-mm Wafer Fab - S. Ikeda, K. Nemoto, and M. Funabashi (Trecenti Technologies Inc.) |
| 16:25 | |
Ten-Minute Intermission |
| 16:35 | 959 |
The Impact of Single Wafer Processing on Process Integration - R. Singh, M. Fakhruddin, and K. Poole (Clemson University) |
| 17:00 | 960 |
Advanced Multilevel Interconnects Technologies for 40-nm Lg Devices - T. Ohba (Fujitsu Limited) |
| 17:25 | 961 |
Performance Limitations of Metal Interconnects and Possible Alternatives - K. Saraswat, P. Kapur, and S. Souri (Stanford University) |
| 17:50 | 962 |
Plasma Technologies for Low-k Dry Etching - T. Tatsumi (Sony Corporation) |
| 18:15 | 963 |
A Novel Approach to Contact Integration at 90-nm and Beyond - A. Singhal, T. Sparks, K. Strozweski, F. Huang, S. Parihar, J. Schmidt, B. Boeck, J. Fretwell, G. Yeap, V. Sheth, S. Veeraghavan, and B. Melnick (Motorola, Inc.) |
Tuesday, April 29, 2003
Co-Chairs: J. Murota and E.X. Ping
| Time | Abs# | Title |
|---|
| 8:00 | 964 |
BiCMOS Integration of High-Speed SiGe:C HBTs - H. Ruecker, B. Heinemann, R. Barth, D. Knoll, D. Schmidt, and W. Winkler (IHP) |
| 8:25 | 965 |
Applications of Silicon Germanium Electrodes in VLSI - E.-X. Ping, E. Blomiley, and F. Gonzalez (Micron Technology, Inc.) |
| 8:50 | 966 |
Noise Properties and Hetero-Interface Trap in SiGe-Channel pMOSFETs - T. Tsuchiya (Shimane University) and J. Murota (Tohoku University) |
| 9:15 | 967 |
Ultra-shallow Junction Formation by Low Energy Ion Implantation and Flash Lamp Annealing - K. Suguro, T. Ito, T. Itani, and T. Iinuma (Toshiba Corporation) |
| 9:40 | |
Ten-Minute Intermission |
| 9:50 | 968 |
New Characterization Techniques for SOI and Related Devices - S. Okhonin, M. Nagoga, and P. Fazan (Swiss Federal Institute of Technology) |
| 10:15 | 969 |
Single and Few Electron Devices. Integration Trends - J. Gautier (CEA-DRT) |
| 10:40 | 970 |
Achieving Low Junction Capacitance on Bulk Si MOSFET Using SDOI Process - Z. Wang, T. Abbott, J. Trivedi, C.-C. Cho, and M. Violette (Micron Technology Inc.) |
| 10:55 | 971 |
Differential Silicide Thickness for ULSI Scaling - W. Taylor, J. Smith, J.-Y. Nguyen, R. Rai, O. Adetutu, J. Geren, J. Ybarra, and D. Petru (Motorola) |
| 11:10 | 972 |
High-Voltage CMOS and Scaling Trends - H. Ballan (Advanced Silicon S.A) |
| 11:35 | 973 |
Emerging Device Solutions for the Post-classical CMOS Era - K. De Meyer (IMEC) |
Co-Chairs: K. Saraswat and J. Borland
| Time | Abs# | Title |
|---|
| 13:40 | 974 |
Modeling End-of-the Roadmap Transistors - A. Asenov (The University of Glasgow) |
| 14:05 | 975 |
Thin Film Transistors in ULSI –Status and Future - Y. Kuo (Texas A and M University) |
| 14:30 | 976 |
Extending The Life Of Planar Single-Gate CMOS and The Realization Of Double-Gate/Multi-Gate CMOS Devices - J. Borland (Varian Semiconductor Equipment Associates), H. Iwai (Tokyo Institute of Technology), W. Maszara (Advanced Micro Devices), and H. Wang (Taiwan Semiconductor Manufacturing Company) |
| 14:55 | |
Ten-Minute Intermission |
| 15:05 | 977 |
Cleaning for Sub 0.1 Micron Technology: A Particular Challenge - M. Knotter (Philips Semiconductors) |
| 15:30 | 978 |
Si Channel Surface Dependence of Electrical Characteristics in Ultra-Thin Gate Oxide CMOS - H. Momose (Toshiba Corporation) |
| 15:55 | 979 |
Integration Issues with High k Gate Stacks - C.M. Osburn, S.K. Han, I. Kim (NC State University), S. Campbell (University of Minnesota), E. Garfunkel, and T. Gustafson (Rutgers University) |
| 16:20 | 980 |
Compatibility of PolySilicon with HfO_2-based Gate Dielectrics for CMOS Applications - V. Kaushik (International Sematech), S. De Gendt, M. Caymax, S. Van Elshocht, A. Delabie, M. Claes, E. Rohr, R. Carter, Y. Manabe (Inter-university MicroElectronic Center (IMEC)), E. Young (International Sematech), M. Schaekers, X. Shi, T. Conard, and M. Heyns (Inter-university MicroElectronic Center (IMEC)) |
| 16:35 | 981 |
Analysis of CMOS Gate-to-Drain Leakage Current and Proposition of a New Cobalt Salicide Selective Etch Chemistry for High DRAM Yield - B. Froment, C. Regnier, and M.-T. Basso (STMicroelectronics) |
| 16:50 | 982 |
Physical Analysis and Modeling of Plasma Etching Mechanism for ULSI Application - M. Kanoh, S. Onoue, K. Nishitani, T. Shimmura, K. Iyanagi, S. Kinoshita, and S. Takagi (Toshiba Corporation) |
| 17:15 | 983 |
Process Strategy for Built-in Reliability of Cu Damascene Interconnect System for 0.13um-Node and Beyond - H. Yamaguchi, T. Oshima, J. Noguchi, K. Ishikawa, H. Aoki, T. Saito (Hitachi, Ltd.), T. Furusawa, and K. Hinode (Hitachi, Ltd.,) |
| 17:40 | 984 |
Impact of Wafer Backside Cu Contamination to 0.18 um Node Devices - S.Q. Gu, L. Duong, J. Elmer, and S. Prasad (LSI Logic) |
| 17:55 | 985 |
Integrated Multiscale Process Simulation of Damescene Structures - M. Bloomfield, Y.H. Im, J. Seok, C. Sukam, J. Tichy, and T. Cale (Rensselaer Polytechnic Institute) |
| 18:10 | 986 |
An Analysis of the Effect of the Steps for Isolation Formation on STI Process Integration - A. Pavan, D. Brazzelli, M. Aiello, C. Capolupo, C. Clementi, C. Cremonesi, and A. Ghetti (STMicroelectronics) |
Hall Maillot, Level 2, Le Palais des Congres
Technical Exhibit and Tuesday Evening Poster Session
| Time | Abs# | Title |
|---|
| o | 987 |
Electrical Characteristics and Thermal Stability of W2N/Ta2O5/Si MOS Capacitors in Nitrogen or Hydrogen Ambient - P. Jiang and J. Chen (National Cheng Kung University) |
| o | 988 |
The Crystallization Behavior and Interfacial Reaction of Ge2Sb2Te5 Thin Films Between Dielectric Material for the Application to the Phase Change Memory - E. Jung, S.-K. Kang, B. Min, and D.-H. Ko (Yonsei University) |
| o | 989 |
Electrodeposition of Low-Dimensional Phases on Au Studied by EQCM and XRD - C. Shannon (Auburn University) |
| o | 990 |
Effects of Nitridation-treatment for Electrical Properties of MONOS Nonvolatile Memories - H. Aozasa, I. Fujiwara, K. Nomoto, H. Komatsu, and T. Kobayashi (Sony Corporation) |
| o | 991 |
Study of Sub-Quartet-Micron PMOSFET NBTI Under DC and AC Stress - E. Li, S. Prasad, S. Park, and J. Walker (LSO Logic Corporation) |
| o | 992 |
Defect Generation and Suppression in Device Processes Using a Shallow Trench Isolation Scheme - D. Peschiaroli, M. Brambilla, G.P. Carnevale, A. Cascella, F. Cazzaniga, C. Clementi, C. Cremonesi, A. Gilardini, M. Martinelli, A. Maurelli, I. Mica, A. Pavan, G. Pavia, F. Piazza, M.L. Polignano (ST Microelectronics), and E. Bonera (INFM-MDM) |
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