Layers of Logic Produce Skyscraper Chips

Stanford engineers have created a four-layer prototype high-rise chip. The bottom and top layers are transistors, which are sandwiched between two layers of memory.
Credit: Max Shulaker, Stanford

Cheaper, smaller, and faster – those are the three words we’re constantly hearing when it comes to innovation and development in electronics. Now, Stanford University engineers are adding a fourth word to that mantra – taller.

The Stanford team is about to reveal how to build a high-rise chip that could vault the performance of the single-story logic and memory chips on today’s circuit cards – thereby preventing the wires connecting logic and memory from jamming.

This from Stanford University:

The Stanford approach would end these jams by building layers of logic atop layers of memory to create a tightly interconnected high-rise chip. Many thousands of nanoscale electronic “elevators” would move data between the layers much faster, using less electricity, than the bottleneck-prone wires connecting single-story logic and memory chips today.

Read the full article here.

The new research leverages three main breakthroughs. First, it provides new technology for creating transistors. Second, the research produces a new type of computer memory that lends itself to multi-story fabrication. Finally, a new technique for building logic and memory technologies is provided.

“This research is at an early stage, but our design and fabrication techniques are scalable,” said lead engineer of the research, Subhasish Mitra. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.”

ECS’s Digital Library has a vast array of research, including all things solid state and electrochemical. Take a look at the research our scientist are doing with chips.


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