The Electrochemical society hosted “Epitaxial Si/SiGe Multilayers for novel logic and memory devices” a live webinar by Roger Loo (imec) on May 6, 2026. A live question and answer session followed. Answers to some of the questions not addressed during the broadcast follow.
Replay webinarQ&A
How do you avoid TSVs (thru silicon vias)?
This presentation did not cover the post epi device fabrication steps. For this question, we kindly refer the audience to the work published by Anabela Veloso et al 2024 ECS Trans. 113 13, https://iopscience.iop.org/article/10.1149/11302.0013ecst










