Q&A on New Epitaxial Growth Technology

ECS Journal of Solid State Science and TechnologyIn a recently published ECS Journal of Solid State Science and Technology paper, ECS member Roger Loo and coauthors describe a new epitaxial growth technology and address the challenges of implementation. The open access article, “Epitaxial CVD Growth of Ultra-Thin Si Passivation Layers on Strained Ge Fin Structures,” was designated Editors’ Choice due to its significance and the importance of the technology described.

“The work combines carefully thought out and elegant experimental work, with appropriate simulation work that compliments the experiments,” said Jennifer Bardwell, ECS Journal of Solid State Science and Technology technical editor in the area of electronic materials and processing. “I am certain that it will be of great interest to many of our readers.”

We recently sat down with Loo to discuss the work and its impact on the field.

The Electrochemical Society: What is novel about this work? Why do believe it received the designation of Editors’ Choice?

Roger Loo: We described a new epitaxial growth technology of ultrathin Si layers on narrow Ge fins or on Ge nanowires to passivate (strained) Ge surfaces in the high-k gate module. A novel Si precursor (tetra-silane) was used to increase epitaxial growth rate from device fabrication point of view, which required extremely low growth temperatures.

We also addressed important challenges when implementing the epitaxial growth scheme in advanced Ge device fabrication schemes. Key issues which have been addressed in this manuscript are the Ge segregation suppression in order to reduce Dit, growing the Si capping layer as thin as possible to simultaneously obtain high carrier mobility, low CET while maintain good CV characteristic, and controlling the strain in Ge channels. We described the root cause for the surface reflow of strained Ge fins as observed after the deposition of the Si passivation layer, supported by three dimensional atomistic modelling. The Ge surface reflow is strongly affected by the strength of the H-passivation during Si-capping and we demonstrated how it can be avoided by carefully selected process conditions.

ECS: What makes this type of fundamental research so important? How does it impact application?

RL: The manuscript is application driven combined with a strong focus on fundamental understanding of the epitaxial growth scheme and surface diffusion phenomena. This research activity resulted in a better understanding of the low temperature Si growth process, the benefits and limitations of novel Si precursors, and understanding of strain relaxation mechanism as seen for narrow strained Ge fins.

ECS: How could your work impact future research in the field of electronic materials and processing?

RL: This study will help to define the optimal high-k gate module fabrication scheme when using Ge channels.

ECS: Where do you hope to see this research go in the future?

RL: A lot of effort has been done to implement this epitaxial growth scheme in strained Ge fin fabrication schemes. First steps have been made to implement this scheme in the fabrication of horizontal Ge nanowires. Promising results have been achieved for pFET devices. For nFET devices, a further reduction of the interface trap density is required.

Another challenge is the deposition of the Source/Drain material. A further increase of active doping concentration is required to continue device scaling. The need to increase the active S/D doping is especially a concern for Ge channel devices. Because of the low dopant solubility, it is extremely challenging to fabricate S/D contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. This requires further research on novel material fabrication schemes.


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