203rd Meeting - Paris, France

April 27-May 2, 2003


J3 - Eleventh International SOI Device Technologies


Wednesday, April 30, 2003

Room 252A, Level 2, Le Palais des Congres

SOI Materials

Co-Chairs: S. Cristoloveanu and C. Mazure

8:00809 The SOI Odyssey - P. Hemment (University of Surrey)
8:30810 Quality Improvement of SIMOX Wafers by Utilizing Nitrogen-doped Cz Si Crystal - K. Kawamura, I. Hamaguchi, T. Sasaki, S. Takayama, Y. Nagatake, and A. Matsumura (Wacker NSCE Corporation)
9:00811 Development of SiC Substrate with Buried Oxide Layer for Electron-Photon Merged Devices - M. Nakao (Osaka Prefecuture University), S. Hirai (Hosiden Corporation), and K. Izumi (Osaka Prefecuture University)
9:20812 A Study on Selective Si0.8Ge0.2 Etch Using Polysilicon Etchant Diluted by H2O for Three-Dimensional Si Structure Application - S.-M. Kim, C.-W. Oh, J.-D. Choe, C.-S. Lee, and D. Park (Samsung Electronics Co. Ltd)
9:40 Twenty-Minute Intermission
10:00813 Relaxed SiGe-On-Insulator Substrates Through Implanting Oxygen into Pseudomorphic SiGe/Si Heterostructure - M. Zhang, Z. An (Shanghai Institute of Microsystem and Information Technology), P. Chu (City University of Hong Kong), and C. Lin (Shanghai Institute of Microsystem and Information Technology)
10:20814 Status Of 300 mm SOI Material; Comparisons With 200 mm - H. Hovel, M. Almonte, P. Tsai, J. Lee, S. Maurer, R. Kleinhenz, D. Schepis, R. Murphy, P. Ronsheim, A. Domenicucci, J. Bettinger, and D. Sadana (IBM Corporation)
10:40815 Replacing the BOX with Buried Alumina: Improved Thermal Dissipation in SOI MOSFETs - K. Oshima (CEA Grenoble), S. Cristoloveanu (IMEP), B. Guillaumot (STMicroelectronics), G. Le Carval (CEA Grenoble), H. Iwai (Tokyo Institute of Technology), C. Mazure (SOITEC), M.-S. Kang (COMTECS), Y.-H. Bae (Uiduk University), J.-W. Kwon, and J.-H. Lee (Kyungpook National University)
11:00816 Studies on Novel SOI-Structure with AlN Film as Buried Insulator - C. Lin, M. Zhu, C. Men, Z. An, and M. Zhang (Chinese Academy of Sciences)
11:20817 Silicon-on-Insulator-Multilayer Structure Fabricated by Epitaxial Layer Tranfer - W. Liu, X. Xie, Q. Lin, Z. Zhang, and C. Lin (Shanghai Institute of Microsystem and Information Technology)
11:40818 Scaling Analysis of AFM Images for Roughness Evolution during Oxidation of Splitted SOI Wafers - V. Popov and D. Kilanov (Institute of Semiconductor Physics)

Thursday, May 1, 2003

SOI Devices and Double-Gate Transistors

Co-Chairs: F. Gamiz and Y. W. Kim

8:00819 Ultralow-Power FD-SOI Design for Future Mobile Systems - T. Douseki and H. Kyuragi (NTT Corporation)
8:30820 Novel Memory Concepts on SOI - P. Fazan, S. Okhonin, M. Nagoga (Swiss Federal Institute of Technology), R. Ferrant, O. Rey, and A. Borschberg (Innovative Silicon S.A.)
9:00821 A Novel CMOS Memory Cell Architecture for Ultra-Low Power Applications Operating up to 280°C - D. Levacq (Universite Catholique de Louvain), V. Dessard (CISSOID s.a.), and D. Flandre (Universite Catholique de Louvain)
9:20822 High-Voltage Super-Junction SOI-LDMOSFETs with Reduced Drift Length - J.M. Park, T. Grasser, and S. Selberherr (Technical University of Vienna)
9:40 Twenty-Minute Intermission
10:00823 Real Space Transfer Devices in SOI - S. Luryi (State University of New York at Stony Brook)
10:30824 Issues in High Performance FinFET and FDSOI Transistor Design - J. Kedzierski (IBM), M. Ieong, and E. Nowak (IBM Microelectronics)
11:00825 Investigation of Charge Control Related Performances in Double-Gate SOI MOSFETs - V. Kilchytska, M. Chung, J.-P. Raskin, D. Flandre (Universite Catholique de Louvain), H. van Meer, and K. de Meyer (IMEC)
11:20826 Substrate Bias Effects in SOI FinFETs - J. Pretet (STMicroelectronics/IMEP), F. Dauge (IMEP/ENSERG), A. Vandooren, L. Mathew, B.-Y. Nguyen (Digital DNA Laboratories), J. Jomaah, and S. Cristoloveanu (IMEP/ENSERG)
11:40827 Impact of the Graded-Channel Architecture on Double Gate Transistors for High-Performance Analog Applications - M.A. Pavanello, J.A. Martino (Universidade de Sao Paulo), T.M. Chung, A. Kranti, J.-P. Raskin, and D. Flandre (Universite Catholique de Louvain)

Device Physics and Modeling

Co-Chairs: S. Luryi and J. Kedzierski

13:40828 Reduction of Pass-Gate Leakage by Silicon-Thickness Thinning in Double-Gate MOSFETs - W. Sakamoto, T. Endoh, H. Sakuraba, and F. Masuoka (Tohoku University)
14:00829 Device Models for Silicon-On-Insulator (SOI) Insulated-Gate Pn-Junction Devices for Electrostatic Discharge (ESD) Protection Circuit Design - Y. Omura and S. Wakita (Kansai University)
14:20830 Evidence for a "Linear Kink Effect" in Ultra-thin Gate Oxide SOI n-MOSFETs - A. Mercha, E. Simoen, J.-M. Rafi, C. Claeys (IMEC), N. Lukyanchikova, M. Petrichuk, and N. Garbar (Institute of Semiconductor Physics)
14:40831 Strained Si/SiGe Channels: A New Performance Advantage for PD/SOI CMOS - W. Zhang and J.G. Fossum (University of Florida)
15:00832 Electron Mobility in Strained-Si Inversion Layers Grown on SiGe-on-Insulator Substrates - F. Gamiz, J.B. Roldan, and A. Godoy (Universidad de Granada)
15:20833 Accurate and Efficient Method for Accelerated History Effect Simulations - T. Poiroux, G. Labourey (CEA-DRT), P. Flatresse (STMicroelectronics), O. Faynot, M. Belleville (CEA-DRT), and D. Souil (STMicroelectronics)
15:40 Twenty-Minute Intermission
16:00834 Microscopic Theory of Nanoscale SOI MOSFETs - T. Walls, V. Sverdlov, and K. Likharev (Stony Brook University)
16:20835 Comparison of Partially and Fully Depleted SOI Transistors Down to the Sub 50nm Gate Length Regime - L. Dreeskornfeld, J. Hartwich, E. Landgraf, H. Luyken, W. Rosner, T. Schulz, M. Stadele (Infineon Technologies), D. Schmitt-Landsiedel (Technical University of Munich), and L. Risch (Infineon Technologies)
16:40836 Saturation Current Model for the N-channel G^4-FET - B. Dufrene, B. Blalock (The University of Tennessee), S. Cristoloveanu (IMEP), M. Mojarradi, and E. Kolawa (Jet Propulsion Laboratory)
17:00837 SOI Thermal Resistance and Its Application to Thermal Modeling of SOI MOSFETs - M.-C. Cheng and F. Yu (Clarkson University)
17:20838 Quasi-Three-Dimensional Device Simulation of Fully Depleted MOSFET/SOI Focused on Surface Roughness - M. Nakao, H. Iikawa, and K. Izumi (Osaka Prefecture University)
17:40839 Oxidation Simulation of Silicon Nanostructure on Silicon-on-Insulator Substrates - M. Uematsu, H. Kageshiwa (NTT Basic Research Labs), and K. Shirashi (University of Tsukuba)

Level 2 Hallway, Le Palais des Congres

Thursday Evening Poster Session

o840 An Accurate Model for Threshold Voltage and S-factor of Partially-Depleted Surrounding Gate Transistor(PD-SGT) - Y. Yamamoto, M. Hioki, R. Nishi, H. Sakuraba, and F. Masuoka (Tohoku University)
o841 The Nanoscale Double-Gate MOSFET for Analog Applications - D. Jimenez (Universitat Autonoma de Barcelona), B. Iniguez (Universitat Rovira i Virgili), J. Sune (Universitat Autonoma de Barcelona), and J.J. Saenz (Universidad Autónoma de Madrid)
o842 Study of the Leakage Drain Current in Graded-Channel SOI nMOSFETs at High-Temperatures - M. Bellodi and J.A. Martino (Laboratorio de Sistemas Integraveis da Escola Politecnica da USP)
o843 The Benefit of SOI Technologies for Low-Voltage RFID applications - P. Villard, J. De Pontcharra, B. Gomez (LETI-CEA), D. Save (GEMPLUS), S. Choutau, and J. Jomaah (IMEP)
o844 Back-end Analysis of SOI Substrates Incorporating Metallic Layers using a Novel Non-destructive Picosecond Ultrasonic Technique - M. Bain (Queens University Belfast), N. McCusker (Rudolph Technologies), P. McCann, A. Nevin (Analog Devices Belfast), and H. Gamble (Queens University Belfast)
o845 Modeling of Coulomb Scattering of Electrons in Ultrathin Symmetrical DG SOI Transistor - J. Walczak and B. Majkusiak (Warsaw University of Technology)
o846 Estimation of Oxygen Dose by Spectroscopic Ellipsometry and Investigation of Oxide Formation Mechanism by FT-IR for 16O+-Implanted Si Wafers - H. Iikawa, M. Nakao, and K. Izumi (Osaka Prefectture University)
o847 Characteristics of Two Types of MEMS Resonator Structures in SOI Applications - S. Myllymaki, E. Ristolainen, P. Heino, A. Lehto, and K. Varjonen (Tampere University of Tecnology)
o848 1D Quantum-Mechanical Effects on the Carrier Concentration Distribution, Threshold Voltage and Gate-Channel Capacitance in the Double-Gate MOSFETs - F. Dauge, J. Jomaah, and G. Ghibaudo (IMEP)
o849 Carrier Lifetimes in SOI Material - H. Hovel (IBM Corporation)
o850 Comparison of SOI, Poly-Si TFT and Bulk Si MOS Performance Using Gm/ID Methodology - K. Takatori (NEC Corporation) and D. Flandre (Universite Catholique de Louvain)
o851 Analysis of HALO Implant Influence on the Self-Heating and Self-Heating Enhanced Impact Ionization on 0.13 um Floating-Body Partially-Depleted SOI MOSFET at Low Temperature - M.A. Pavanello, J.A. Martino (Universidade de Sao Paulo), E. Simoen, C. Claeys, H. van Meer, and K. De Meyer (IMEC)
o852 Spectroscopic Ellipsometry Characterization of the Interfacial Roughness in Thin SIMOX Wafer - W.J. Li and Y.H. Yu (Chinese Academy of Sciences)

Friday, May 2, 2003

Room 252A, Level 2, Le Palais des Congres

Characterization Techniques and Reliability Issues

Co-Chairs: K. Izumi and S. Krishnan

8:00853 Changes in the Parameters of Silicon-on-Insulator Structures unider Irradiation - I.V. Antonova, D.V. Nikolaev, O.V. Naumova, V.P. Popov (Institute of Semiconductor Physics), and S.A. Smagulova (Yakutsk University)
8:20854 Extraction of High Frequency Noise Parameters of 0.25µm Partially Depleted Silicon-On-Insulator MOSFET : Impact of the High Resistivity Substrate - R. Daviot, O. Rozeau (LETI), S. Chouteau (IMEP - ENSERG), J. De Pontcharra (LETI), and N. Abouchi (CPE Lyon)
8:40855 Temperature and Magnetic Field Dependence of the Carrier Mobility in SOI Wafers by the Pseudo-MOSFET Method - C. Rossel, D. Halley (IBM Research), and S. Cristoloveanu (Institute of Microelectronics, Electromagnetism and Photonics)
9:00856 Steady-State Characterization of Partially Depleted SOI CMOS Gates - A. Bracale, E. Dupont-Nivet, and J.-L. Pelloie (SOISIC)
9:20857 Feasibility of Surface Photovoltage Based Characterization of Ultra-Thin SOI Wafers - L. Lukasiak (Warsaw Unviersity of Technology), E. Kamieniecki (QC Solutions Inc.), A. Jakubowski (Warsaw Unviersity of Technology), and J. Ruzyllo (Pennsylvania State University)
9:40 Twenty-Minute Intermission
10:00858 Analysis of Soft Errors in Floating Channel type Surrounding Gate Transistor (FC-SGT) DRAM Cells - F. Matsuoka and F. Masuoka (Tohoku University)
10:20859 Radiation Damage in Deep Submicron Partially Depleted SOI CMOS - E. Simoen, J.-M. Rafi, A. Mercha, X. Serra-Gallifa, H. van Meer, K. De Meyer, C. Claeys (IMEC), M. Kokkoris, E. Kossionides, and G. Fanourakis (NCSR Demokritos)
10:40860 Radiation Response of SOI CMOS Transistors/4M SRAMs Fabricated in UNIBOND Substrates - M. Liu, W. Heikkila, K. Golke, B. Stinger, M. Flanery, A. Hurst, G. Panning, G. Kirchner (Honeywell SSEC), and W. Jenkins (Naval Research Laboratory)
11:00861 Control of SEU in SOI SRAMs Through Carrier Lifetime Engineering - S. Mitra, D.P. Ioannou (George Mason University), S.T. Liu (Honeywell, SSEC), and D.E. Ioannou (George Mason University)
11:20862 Radiation Hardness of Double-Gate Ultra-Thin SOI MOSFETs - C.R. Cirba (Vanderbilt University), S. Cristoloveanu (IMEP), R.D. Schrimpf, and K.F. Galloway (Vanderbilt University)
11:40863 Nature of High-Temperature Charge Instability of Fully Depleted SOI MOSFETs - A.N. Nazarov, V.S. Lysenko (Institute of Semiconductor Physics), J.P. Colinge (University of California, Davis), and D. Flandre (University Catholique de Louvain)

SOI Materials and Devices

Co-Chairs: G. Celler and P. Hemment

13:50864 Ultrathin SOI Wafers Fabrication and Metrology - C. Maleville (SOITEC)
14:20865 Defects and Electrical Consequences in SOI Buried Oxides - H. Hovel, M. Almonte, J. Lee, D. Sadana, A. Domenicucci, and J. Bettinger (IBM Corporation)
14:40866 Very Low Schottky Barrier to N-Type Silicon with PtEr-Stack Silicide - X. Tang (Universite Catholique de Louvain), J. Katcki (Institute of Electron Technology), E. Dubois (Institut d'Electronique de Microelectronique et de Nanotechnologie), and V. Bayot (Universite Catholique de Louvain)
15:00867 Figures-of-Merit of Intrinsic, Standard-Doped and Graded-Channel SOI and SOS MOSFETs for Analog Baseband and RF Applications - D. Levacq (Universite Catholique de Louvain), M. Dehan (Microwave Laboratory), D. Flandre (Universite Catholique de Louvain), and J.-P. Raskin (Microwave Laboratory)
15:20868 Comparative Study of the Dynamic Performance of Bulk and FDSOI MOSFET by means of a Monte Carlo Simulation - R. Rengel, D. Pardo, and M.J. Martin (University of Salamanca)
15:40869 Threshold Voltage Quantum Simulations for Ultra-Thin Silicon-On-Insulator Transistors - J. Lolivier, S. Deleonibus (CEA-DRT - LETI/DTS), and F. Balestra (IMEP-ENSERG)

Wednesday, April 30, 2003

Co-Chairs: J. Fossum and P. Fazan

13:40870 60-nm Gate Length SOI CMOS Technology Optimized for System-on-a-SOI-Chip Solution - K. Imai, S. Maruyama, T. Suzuki, T. Kudo, S. Miyake, M. Ikeda, T. Abe, S. Masuda (NEC Electronics), A. tanabe, J.-W. Lee (NEC Corporation), K. Shibahara, S. Yokoyama (Hiroshima University), and H. Ooka (NEC Electronics)
14:10871 Emerging Silicon-On-Nothing (SON) Devices Integration - S. Thomas and M. Stephane (STMicroelectronics)
14:40872 Strained-Si/SiGe-on-Insulator CMOS Technology - S.-I. Takagi, T. Mizuno, T. Tezuka, N. Sugiyama, T. Numata, K. Usuda, Y. Moriyama, S. Nakaharai, J. Koga, A. Tanabe (Association of Super-Advanced Electronics Technology), and T. Maeda (National Institute of Advanced Industrial Science and Technology)
15:10873 Extremely Scaled FinFETs and Ultra-Thin Body SOI CMOS Devices - L. Chang, Y.-K. Choi, D. Ha, J. Lee, P. Ranade, S. Xiong, J. Bokor, C. Hu, and T.-J. King (University of California)
15:40 Twenty-Minute Intermission
16:00874 Fully Depleted SOI Process and Device Technology for Digital and RF Application - F. Ichikawa, Y. Nagatomo, N. Hirashita, Y. Katakura, S. Itou, and H. Matsuhashi (Oki Electric Industry Co., Ltd.)
16:30875 Status and Development of Future PD/SOI MOSFETs - S. Krishnan (Advanced MicroDevices)
17:00876 Multi-Fin Double-Gate MOSFET Fabricated by Using (110)-Oriented SOI Wafers and Orientation-Dependent Etching - Y. Liu, K. Ishii, T. Tsutsumi, M. Masahara, H. Takashima, and E. Suzuki (National Institute of Advanced Industrial Science and Technology)
17:20877 Optimization of Ultra-Thin Body, Fully-Depleted SOI Device, with Raised Souce Drain - J. Egley, A. Vandooren, B. Winstead, B. White, and B.-Y. Nguyen (Motorola Inc.)
17:40878 Partially Depleted SOI Dynamic Threshold MOSFET for Low-Voltage and Microwave Applications - M. Dehan, J.-P. Raskin, and D. Vanhoenacker-Janvier (Universite Chatolique de Louvain)


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