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ECS Short Courses

 

Phoenix, AZ | Sunday, May 18, 2008

Short Course #2
Electrical Characterization and Characteristics of MOS Devices
with Ultrathin (0.5-1.5 nm) High-k Gate Dielectrics
Samares Kar, Instructor

This course is designed to accommodate a diverse group of attendees: chemists, physicists, material scientists, electrical engineers, and chemical engineers; hence will begin with the fundamentals, but, end with a discussion of the current issues and the future directions.

The objective of this course is to provide the participants the basic principles and the practical aspects of the electrical characterization techniques for MOS devices with high-k gate dielectrics and an understanding of the important issues of gate dielectric leakage, mobility degradation, gate dielectric degradation, instability, and device reliability. This course will address the following topics and issues:

  • basic analysis of MOS gate structures, including energy band diagrams, circuit representations, and admittance characteristics;
  • limiting thinness of gate dielectrics;
  • effects of carrier confinement, wave function penetration, and tunneling current on accumulation and strong inversion capacitance;
  • important electronic parameters of high-Κ gate dielectrics and correlation between these parameters;
  • origin of interface and bulk dielectric traps;
  • extraction of gate dielectric capacitance, flat-band voltage, channel doping density, surface potential, dielectric potential, threshold voltage, interface trap density and capture cross-section, and tunneling electron/hole mass;
  • non-contact electrical characterization;
  • determination of channel mobility;
  • model of the gate dielectric stack with three layers and four interfaces;
  • analysis of the interface trap charges, bulk trap charges, electric fields, and potentials across a gate dielectric stack, and the influence of these on gate leakage current and on device reliability;
  • mobility and threshold voltage degradation;
  • negative bias temperature instability; and
  • metal work-function pinning.

 

About the Instructor

Samares Kar’s seminal work on ultrathin (2-4 nm) SiO2 gate dielectrics, carried out some three decades ago, provides some of the basic physics and characterization tools for future generation MOS nano-transistors. His research interests have included MOS tunnel devices, Si-SiO2 and Si/high-k interface states, high-k gate dielectrics, MOS/MIS parameter extraction, process induced defects, and organic monolayers.

Dr. Kar was the lead organizer of the First, Second, and Third International Symposia on High Dielectric Constant Gate Stacks held respectively in October 2002 in Salt Lake City, UT, in October 2003 in Orlando, FL, and in October 2005 in Los Angeles, CA.

Dr. Kar is an Emeritus Fellow of Electrical Engineering in the Indian Institute of Technology, Kanpur, where he joined in 1974 and was a Professor of Electrical Engineering during 1980-2004. He has studied in India and USA, and worked in India, USA, and West Germany.

For additional information about Education, please contact: education @electrochem.org

 
 

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