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ECS Short Courses


Vancouver, Canada | Sunday, April 25, 2010

Short Course #4
Interfaces, Traps, and Defects in Gate Stacks
Samares Kar, Instructor

This course is designed to accommodate a diverse group of attendees: chemists, physicists, material scientists, chemical engineers, and electrical engineers; hence it will begin with the basics, and end with a discussion of the current issues and future directions. The objective of this course is to provide the participants with the basic principles and the practical aspects of the large variety of interfaces occurring in gate stacks on silicon, germanium, and III-V compound semiconductor substrates; and the defects and electron/hole traps likely to be found in the different interfaces and the bulk layers of the gate stack and the channel. This course will address the following topics and issues:

  • various constituent layers and interfaces of the gate stack;
  • model of the gate stack with two bulk layers and three interfaces;
  • thermodynamic stability of the different interfaces;
  • chemical reactions occurring at the interfaces;
  • interlayer diffusion of atoms and ions across the interfaces;
  • nature of the chemical bonds at the interfaces;
  • chemical profiles of atoms across the interfaces;
  • passivation of germanium and III-V compound semiconductor surfaces;
  • nature of oxygen vacancies in the different bulk layers;
  • other types of defects in the gate stack;
  • origin and nature of the interface and bulk layer electron/hole traps, their energy levels, density distribution, and capture cross-sections;
  • analysis of the interface trap charges, bulk trap charges, electric fields, and potentials across a gate stack;
  • flat-band voltage roll-off;
  • metal Fermi level pinning; and
  • most crucial defects and traps from the point-of-view of gate stack reliability.


About the Instructor

Samares Karís seminal work on ultrathin (2-4 nm) SiO2 gate dielectrics, carried out some four decades ago, provides some of the basic physics and characterization tools for current and future generation MOS nanotransistors. His research interests have included MOS tunnel devices, Si-SiO2 and Si/high-k interface states, high-k gate dielectrics, MOS/MIS device parameter extraction, process induced defects, solar cells, organic monolayers, and RFID.

Dr. Kar was the lead organizer of the first, second, third, fourth, fifth, and sixth International Symposia on High Dielectric Constant Gate Stacks held respectively in October 2002 in Salt Lake City, UT; in October 2003 in Orlando, FL; in October 2005 in Los Angeles, CA; in October 2006 in Cancun, Mexico; in October 2007 in Washington, DC; and in October 2008 in Honolulu, Hawaii.

Dr. Kar is an Emeritus Fellow of Electrical Engineering in the Indian Institute of Technology, Kanpur, where he joined in 1974 and became a Professor of Electrical Engineering in 1980. He has studied in India and the U.S., and worked in India, the U.S., and West Germany.

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