211th ECS Meeting - Chicago, Illinois

May 06 - May 10, 2007

PROGRAM INFORMATION
 

E1 - Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS: New Materials, Processes, and Equipment 3

Electronics and Photonics/Dielectric Science and Technology/High Temperature Materials
 

Monday, May 7, 2007

Boulevard C, 2nd Floor

Key Note Address

Co-Chairs: E. Gusev and F. Roozeboom
TimeAbs#Title and Authors
10:30 554 The Future of CMOS -- Limits and Opportunities T. H. Ning (IBM)
 

Advanced CMOS Channel Engineering

Co-Chairs: S. Koester and A. Wei
TimeAbs#Title and Authors
13:50 555 Integration Challenges For Advanced Uniaxially-Strained CMOS on Wafer-Level Biaxial-Strained-SOI (SSOI) A. Wei, T. Kammler (AMD Saxony) and M. Horstmann (AMD)
14:20 556 Correlation of Local Strain in a TEM Sample and in the Bulk for a Recessed SiGe CMOS Structure W. Zhao (North Carolina State University), G. Duscher (North Carolina State University Department of Materials Science and Engineering), M. Zikry and G. Rozgonyi (North Carolina State University)
14:40 557 Origin and Suppression of Junction Leakage in Germanium-On-Silicon Structures C. Claeys, S. Sonde, E. Simoen, A. Satta, B. De Jaeger, G. Nicolas and M. Meuris (IMEC)
15:00 558 A Step Towards a Better Understanding of Silicon Passivated (100)Ge p-Channel Devices G. Pourtois, M. Houssa, B. De Jaeger, F. Leys, B. Kaczer, M. Caymax, M. Meuris, G. Groeseneken and M. Heyns (IMEC)
15:30 559 Influence of Annealing Treatments on the Morphology and Electrical Properties of GeOI Substrates Obtained by Ge Condensation J. Damlencourt (CEA/LETI), Y. Campidelli (STMicroelectronics), B. Vincent (CEA/LETI/D2NT/LFE), T. Nguyen (IMEP-INP Grenoble), C. Le Royer (CEA/LETI/DNT), Y. Morand (STmicroelectronics), S. Cristoloveanu (IMEP-INP Grenoble) and L. Clavelier (CEA/LETI/D2NT)
15:50 560 Gallium Nitride - A Material for Digital Electronics? U. K. Mishra (University of California, Santa Barbara)
16:20 Intermission (20 Minutes)
16:40 561 Silicon Nanowire: Technology Platform, Devices, Applications and Challenges P. Lo, N. Singh, S. Rustagi, N. Balasubmaramian and D. Kwong (Institute of Microelectronics)
17:10 562 GaAs Heteroepitaxy on SiGe-on-Insulator Using Ge Condensation and Migration Enhanced Epitaxy H. Oh, K. Choi (National University of Singapore), W. Loh (Institute of Microelectronics), T. Htoo, S. Chua and B. Cho (National University of Singapore)
17:30 563 Fabrication of InP/SiO2/Si Substrate using Ion-Cutting Process and Selective Chemical Etching P. Chen (University of California, San Diego), S. Lau (University of California San Diego), D. Xu, L. Mawst (University of Wisconsin, Madison) and T. Kuech (University of Wisconsin Madison)
17:50 564 Improved Current Drivability and Gate Stack Integrity using Buried SiC Layer for Strained Si/SiGe Channel Devices H. Zang (National University of Singapore) and W. Loh (Institute of Microelectronics)
 

Tuesday, May 8, 2007

Boulevard C, 2nd Floor

Advanced CMOS Gate Stack Engineering I

Co-Chairs: E. Gusev and M. Takayanagi
TimeAbs#Title and Authors
08:00 565 DyScHfOx as High-κ Gate Dielectrics: Structural and Electrical Properties C. Adelmann, S. Van Elshocht (IMEC), P. Lehnen (AIXTRON), T. Conard (IMEC), A. Franquet (Zhao@imec.be), C. Zhao, L. Ragnarsson, V. Chang, H. Cho, Y. Hong-Yu and S. De Gendt (IMEC)
08:20 566 Influence of Ru Dopant on the Dielectric Properties of Zr-doped HfO2 High-k Thin Film C. Lin (Texas A&M Univ.), Y. Kuo and J. Lu (Texas A&M University)
08:40 567 Scaling Issues in High-k/ Metal Gate Stacks G. Wilk and C. Wang (ASM America)
09:10 568 The Study of Hafnium Silicate by NO Gas Annealing Treatment D. Suh, D. Lee, K. Chung (Yonsei Univ.), M. Cho (Korea Research Institute of Standards and Science) and D. Ko (Yonsei Univ.)
09:30 Intermission (20 Minutes)
09:50 569 Mechanisms of and Solutions to Moisture Absorption of Lanthanum Oxide as High k Gate Dielectric Y. Zhao, K. Kita, K. Kyuno (The University of Tokyo) and A. Toriumi (University of Tokyo)
10:10 570 Investigations of Work Function Shift in Lanthanum Silicate High-k Dielectric MIS Capacitors J. S. Jur, D. Lichtenwalner and A. Kingon (North Carolina State University)
10:30 571 Challenge for High-k/MG CMOSFETs in 32 nm Generation and Beyond M. Takayanagi (Toshiba America Electronic Components, Inc.)
11:00 572 Surface Treatment and Functionalization Effects on Chemical Vapor Deposition and Atomic Layer Deposition Grown HfO2 S. Consiglio (University at Albany), R. Mo, T. Tai, S. Krishnan (IBM Microelectronics), D. O'Meara, C. Wajda (Tokyo Electron America Inc) and M. Chudzik (IBM Microelectronics)
11:20 573 Vacuum UV Spectroscopic Ellipsometry and X-Ray Reflectance Combined on the same Platform for the Characterization of High-k Gate Dielectrics C. Defranoux, A. Bondaz, L. Kitzinger (SOPRA-SA) and J. Piel (SOPRA)
11:40 574 Thermal Stabililty of Atomic Layer Deposited HfO2 Films using Hf([N(CH3)(C2H5)]3[OC(CH3)3]) Precursor and O3 Oxidant M. Seo, S. Kim, T. Park, J. Kim and C. Hwang (Seoul National University)
 

Advanced CMOS Gate Stack Engineering II

Co-Chairs: D. L. Kwong and G. Wilk
TimeAbs#Title and Authors
14:00 575 Theoretical Studies on Metal/High-k Gate Stacks K. Shiraishi (University of Tsukuba), Y. Akasaka (Selete (Present: Tokyo Electron Inc.)), G. Nakamura (Selete (Present: Tokyo Electron Inc.), T. Nakayama (Chiba University), S. Miyazaki (Hiroshima University), H. Watanabe (Osaka University), A. Ohta (Hiroshima University), K. Ohmori, T. Chikyow (National Institute for Materials Science), Y. Nara (Semiconductor Leading Edge Technologies, Inc.), K. Yamabe (University of Tsukuba) and K. Yamada (Waseda University)
14:30 576 Inverse-Vg Dependence of PBTI Lifetime of HfSiON Gate Dielectrics Measured by a High-Temperature Pulsed-IV Method F. Ootsuka, T. Eimori (Selete), Y. Nara (Semiconductor Leading Edge Technologies, Inc.) and Y. Ohji (Selete)
14:50 577 On the Depth Profiling of the Traps in MOSFET's with High-k Gate Dielectrics D. Bauza (IMEP (INP Grenoble, UJF, CNRS)), O. Ghobar (IMEP) and B. Guillaumot (LETI/ST Microelectronics)
15:10 578 Effective Capture Cross-Sections of Traps in High-k Gate Dielectrics L. Song, X. Wang, D. Guo and T. Ma (Yale University)
15:30 Intermission (20 Minutes)
15:50 579 Full Range Work Function Tuning of MOSFETs using Interfacial Yttrium Layer in fully Germanided Ni Gate H. Yu (Singapore-MIT Alliance), K. Pey (Nanyang Technological University), W. Choi (Singapore-MIT Alliance and National University of Singapore), D. A. Antoniadis, G. A. Fitzgerald (Singapore-MIT Alliance and Massachusetts Institute of Technology), M. Dawood, K. Ow (National University of Singapore) and D. Chi (Institute of Materials Research and Engineering)
16:10 580 Low-Temperature Nickel Silicide Formation on SiO2 Films with a Cl Plasma Containing NiCl F. Hirose, N. Fujiwara, S. Ohshima (Yamagata Univiersity), N. Ohyama (Mitsubishi) and H. Sakamoto (Phyzchemics)
16:30 581 Recent Advances in Search for Suitable High-k/Metal Gate Solutions to Replace SiON/Poly-Silicon Gate Stacks in CMOS Devices for 45nm and Beyond Technologies V. Paruchuri, V. Narayanan, L. Barry, E. Cartier, N. Bojarczuk, S. Guha and S. Brown (IBM Research)
17:00 582 Structural and Electrical Properties of High Pressure Hydrogen Post-Annealed Pt-Er Alloy Metal Gate on HfO2 Film C. Choi, M. Jang, Y. Kim, M. Jeon, S. Lee (Electronics and Telecommunications Research Institute (ETRI)), H. Yang, R. Jung (Samsung Advanced Institute of Technology (SAIT)), M. Chang and H. Hwang (Gwangju Institute of Science and Technology (GIST))
17:20 583 Gate Quality Al2O3 by Molecular-Atomic-Deposition (MAD) and its Potential Applications in III-V Semiconductor CMOS Technology S. Cui (Yale University), J. Zheng (Intel Corporation), S. Shim and T. Ma (Yale University)
17:40 584 The effect of Interfacial Layer of High-K Dielectrics on GaAs Substrate Y. Tong and B. Cho (National University of Singapore)
 

Southwest Hall, Lower Level

Tuesday Evening Poster Session

Co-Chairs: H. Iwai and F. Roozeboom
TimeAbs#Title and Authors
o 585 Fabrication of CeO2 Dielectric Films by Chemical Vapor Deposition with a Liquid Metal Organic Source K. Ishibashi (Canon ANELVA Corporation), S. Setsu (Semiconductor Process Laboratory Co,.Ltd.), N. Keiichi, T. Kazunari, O. Masatsugu, S. Kiyotaka and Y. Yasuhiro (Hosei University)
o 586 Structural and Electrical Properties of Er2O3 Thin Films Deposited by RF Sputtering for Gate Dielectric Applications G. C. Deepak and N. Bhat (Indian Institute of Science)
o 588 Excellent Electrical Characteristics of Praseodymium Oxide Dielectrics on Si Substrate by Reactive RF Sputtering T. Pan, C. Hsieh, F. Tsai and T. Wu (Chang Gung University)
o 589 Properties of MOCVD and MOALD Grown TiN Thin Films for Gate Electrode Application K. Frohlich, K. Husekova, M. Rosina, M. Tapajna, E. Dobrocka, A. Rosova (Institute of Electrical Engineering, SAS), J. Espinos (Instituto de Ciencia de Materiales de Sevilla, CSIC), P. Baumann and J. Lindner (AIXTRON A.G.)
o 590 A New Liquid Precursor for Pure Ruthenium Depositions J. Gatineau and C. Dussarrat (Air Liquide Laboratories)
o 591 On the Verification of EEDFs in Plasmas with Silane using Optical Emission Spectroscopy A. Boogaard, A. Kovalgin, A. I. Aarnink, J. Holleman, R. M. Wolters, I. Brunets and J. Schmitz (University of Twente)
o 592 Relaxation of strained Si1-XGeX by Dry Oxidation B. Min (Yonsei University), D. Ko (Yonsei Univ.), M. Cho (Korea Research Institute of Standards and Science) and T. Lee (Ju Sung Engineering Co., Ltd.)
o 593 Nanoscaled Silicon Based Heterostructures Formed by Interface Mediated Endotaxy V. P. Popov, I. Tyschenko and E. Cherkov (Instittute of Semiconductor Physics)
o 594 An Original Selective Etch of Pt vs. PtSi using a Low Temperature Germanidation Process N. Breil (STMicroelectronics - IEMN), A. Halimaoui (STMicroelectronics), E. Dubois, G. Larrieu (IEMN), A. Laszcz, J. Katcki, J. Ratajczak (Institute of Electron Technology), G. Rolland (CEA-LETI), A. Pouydebasque (NXP) and T. Skotnicki (STMicroelectronics)
o 77 Thermodynamic Properties of Trace Water Vapor in High Purity Hydrogen Bromide used for Semiconductor Processing J. Yao, E. Olsen and M. Raynor (Matheson Tri-Gas, Inc.)
o 79 Bendable Integrated Circuits on Plastic Substrates by Use of Printable Single Crystalline Silicon J. Ahn, H. Kim, E. Menard, K. Lee, Z. Zhu, R. Nuzzo and J. Rogers (University of Illinois at Urbana-Champaign)
 

Wednesday, May 9, 2007

Boulevard C, 2nd Floor

Advanced Source/Drain Engineering

Co-Chairs: P. Timans and Y. Kim
TimeAbs#Title and Authors
08:10 595 Mechanistic Understanding of Native Defect Clustering and Annihilation in Complex Si-SiO2 Systems through First Principles-based Atomistic Modeling G. S. Hwang, S. Lee and S. Lee (University of Texas at Austin)
08:30 596 Defect-medicated Mechanisms of N-type Dopant Diffusion in Silicon G. S. Hwang, S. Harrison and K. Kweon (University of Texas at Austin)
08:50 597 Junction Architectures for Planar Devices B. J. Pawlak, R. Duffy (NXP Semiconductors), T. Hoffman (IMEC), S. Felch (Applied Materials), P. Eyben, B. Van Daele and W. Vandervorst (IMEC)
09:20 598 Defect Engineering for Ultrashallow Junctions using Surfaces E. G. Seebauer (University of Illinois), S. Yeong, M. Srinivasan (National University of Singapore), C. Kwok, R. Vaidyanathan (University of Illinois), B. Colombeau (Chartered Semiconductor Manufacturing) and L. Chan (Chartered Semiconductor Manufacturing Ltd)
09:40 Intermission (20 Minutes)
10:00 599 Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production T. Feudel and M. Horstmann (AMD)
10:30 600 Diffraction Originated Local Heating of Nanometer Scale Device Patterns in Lamp-Based Rapid Thermal Annealing W. Yoo and K. Kang (WaferMasters, Inc.)
10:50 601 Relaxation-Induced Excess Leakage Current in Recessed Si1-xGex Source/Drain Junctions C. Claeys, E. Simoen, M. Chowdhury, N. Bhouri, P. Verheyen, F. Leys, O. Richard, R. Loo (IMEC), V. Machkaoutsan, P. Tomasini, S. Thomas (ASM), J. Lu, J. Weijtmans and R. Wise (Texas Instruments)
11:10 602 Growth Kinetics and Boron-Doping of very High Ge Content Si1-xGex for Sources and Drains Engineering J. Hartmann (CEA-LETI, Minatec), F. Gonzatti, J. Barnes and T. Billon (CEA-LETI)
11:30 603 Chlorine for in-situ Low-Temperature Silicon Surface Cleaning for Epitaxy Applications K. H. Chung and J. C. Sturm (Princeton University)
 
Co-Chairs: M. C. Ozturk and T. Feudel
TimeAbs#Title and Authors
14:00 604 Selective Si:C Epitaxy Growth on Recessed Area and Material Properties Characterizations Y. Kim, Z. Ye, A. Lam, A. Zojaji, Y. Cho and S. Kuppurao (Applied Materials)
14:30 605 Defect Free Embedded Silicon Carbon Stressor Selectively Grown into Recessed Source Drain Areas of NMOS Devices M. Bauer, Y. Zhang, D. Weeks (ASM America), V. Machkaoutsan and S. Thomas (ASM)
14:50 Intermission (20 Minutes)
15:10 606 Chemical Vapor Deposition Epitaxy of Silicon and Silicon-Carbon Alloys at High Rates and Low Temperatures using Neopentasilane J. C. Sturm, K. Chung (Princeton University), E. Sanchez, K. K. Singh and S. Kuppurao (Applied Materials)
15:40 607 Dopant Segregated Pt and Ni-Germanide Schottky S/D p-MOSFETs with Strained Si-SiGe Channel H. Zang and C. Chua (National University of Singapore)
16:00 608 NiSi Roughness on Embedded SiGe O. Kwon (Infineon Technologies NA, Hopewell Junction, New York 12533, USA), O. Kwon (IBM SRDC), J. Han (Infineon Technologies NA) and H. Utomo (IBM SRDC)
16:20 609 NiSi for CMOS: Comparison of Phase Transformation Curves for Si and SiGe Substrates Annealed in a Near-Isothermal Cavity I. J. Malik, M. Ouaknine, T. Fukada, T. Ueda, W. Yoo (WaferMasters, Inc.), P. Press and R. Binder (AMD)