211th ECS Meeting - Chicago, Illinois

May 06 - May 10, 2007

PROGRAM INFORMATION
 

E4 - SOI Device Technology 13

Electronics and Photonics
 

Monday, May 7, 2007

Stevens 5, Northwest Hall, Lower Level

Technology, Process Integration, Radiation Hardness

Co-Chairs: G. Celler, K. Endo
TimeAbs#Title and Authors
14:10 Introductory Remarks (10 Minutes)
14:20 705 Embedding Device Solutions in Engineered Substrates C. Mazure (SOITEC)
15:00 706 Physics and Integration of Fully-Depleted Silicon-On-Insulator Devices A. Vandooren (Freescale Semiconductor Inc.)
15:40 Intermission (20 Minutes)
16:00 707 Impact of Metal Silicide Layout Covering Source/Drain Diffusions on Parasitic Resistance of Triple-Gate SOI MOSFET Y. Omura, K. Yoshimoto (Kansai University) and H. Wakabayashi (Sony Corp., Atsugi TEC)
16:20 708 High dose Implantation Impact on the Carrier Mobility in Ultra-Thin Unstrained and Strained SOI Films C. Dupre (CEA/LETI Minatec), P. Fazzini (CEMES), T. Ernst (CEA/LETI Minatec), F. Cristiano (LAAS), A. Claverie (CEMES), J. Hartmann (CEA-LETI, Minatec), F. Andrieu, O. Faynot, P. Rivallin, F. Laugier (CEA/LETI Minatec), G. Ghibaudo (IMEP Minatec), S. Cristoloveanu (IMEP-INP Grenoble) and S. Deleonibus (CEA/LETI Minatec)
16:40 709 Low Temperature Chatacterization of High-k Dielectric Metal Gate FD-SOI nMOSFETs L. Zafari, J. Jomaah (Minatec), G. Ghibaudo (IMEP Minatec), O. Faynot (CEA/LETI Minatec) and A. Vandooren (Freescale Semiconductor Inc.)
17:00 710 Uniaxial Strain Enhancement in SOI Technology for the Improvement of Channel and Exterior Resistances D. Zhang (Freescale Semiconductor), D. Goedeke, V. Dhandapani, J. Hildreth, C. Fu, T. Kropewnicki, A. Lu, M. Jahanbani, H. Martinez, R. Noble, D. Eades, N. Liu, L. Kang, B. Nguyen, V. Kolagunta, M. Hall, J. Cheek and S. Venkatesan (Freescale)
17:20 711 Heavy Ion Upsets in 150nm SOI CMOS SRAMs Fabricated in UNIBOND M. S. Liu, D. K. Nelson, J. C. Tsang (Honeywell International) and H. L. Hughes (Naval Research Laboratory)
 

Tuesday, May 8, 2007

Stevens 5, Northwest Hall, Lower Level

FinFETS and other Devices

Co-Chairs: S. Cristoloveanu, A. Thean
TimeAbs#Title and Authors
08:20 712 Intrinsic Advantages of SOI Multiple-Gate MOSFET (MuGFET) for Low Power Applications W. W. Xiong (Texas Instruments), C. Cleavelin (Texas Intruments, Inc), C. Hsu, M. Ma (UMC), K. Schruefer (Infineon Technologies), P. Patruno (SOITEC) and J. Colinge (University of California, Davis)
09:00 713 Fabrication and Power-Management Demonstration of Four-Terminal Separated-Gate FinFETs K. Endo, Y. Liu, M. Masahara, T. Matsukawa, S. O'uchi and E. Suzuki (National Institute of AIST)
09:40 Intermission (20 Minutes)
10:00 714 Parasitic Effects Depending on Shape of Spacer Region on FinFETs Y. Kobayashi, Y. Kobayashi, K. Tsutsui, K. Kakushima (Tokyo Institute of Technology), V. Hariharan, V. Rao (Indian Institute of Technology), P. Ahmet and H. Iwai (Tokyo Institute of Technology)
10:20 715 Modelling the Back-Gate Coupling effect in Triple-, Π- and Ω-Gate FETs R. Ritzenthaler (LETI - CEA), M. Gaillardin (CEA Saclay), K. Akarvardar (IMEP), O. Faynot (CEA/LETI Minatec), C. Jahan (LETI CEA) and S. Cristoloveanu (IMEP-INP Grenoble)
10:40 716 Origin of Transient Gate Current Observed in Pseudo-MOS Transistor S. Sato (Kansai University), T. Nguyen, S. Cristoloveanu (IMEP-INP Grenoble) and Y. Omura (Kansai University)
11:00 717 Impact of Improved Mobilities and Suppressed 1/f Noise in Fully Depleted SOI MOSFETs Fabricated on Si(110) Surface W. Cheng, W. Cheng, A. Teramoto, C. Tye, P. Gaubert, M. Hirayama, S. Sugawa and T. Ohmi (Tohoku University)
11:20 718 The "C" Shape Behavior of the Floating Body Effect in Function of Temperature in PD SOI nMOSFETs P. G. Agopian (University of São Paulo), J. A. Martino (FEI/USP), E. Simoen and C. Claeys (IMEC)
11:40 719 Hot Carrier Instability Mechanism in Accumulation-Mode Normally-off SOI nMOSFETs and Their Reliability Advantage R. Kuroda, A. Teramoto, W. Cheng, S. Sugawa and T. Ohmi (Tohoku University)
 

TFTs, Photons, Phonons, and Electrons

Co-Chairs: Y. Omura, M. Fischetti
TimeAbs#Title and Authors
14:00 720 ELECTRONICS AND PHOTONICS DIVISION AWARD ADDRESS: Thin Film Transistor and ULSIC Technologies - Parallel or Crossing? Y. Kuo (Texas A&M University)
14:40 721 Integration of SOI-Based 2D- and Si-Based 3D Photonic Crystals C. M. Sotomayor Torres (University College Cork), G. Kocher, W. Khunsin, J. Romero Vivas (University College Cork, Tyndall National Institute), K. Vynck (University of Montpellier II), S. Arpiainen (Technical Research Centre of Finland), S. Romanov (University College Cork, Tyndall National Institute), B. Lange (University of Mainz), M. Mulot (Technical Research Centre of Finland), F. Jonsson (University of Southampton), T. Charvolin, E. Hajdi (DRFMC/SPMM, CEA), D. Cassagne (University of Montpellier II), R. Zentel (University of Mainz) and J. Ahopelto (Technical Research Centre of Finland)
15:20 722 Complementary Single-Crystal Si (110) Thin-Film Transistors on Flexible Plastic Substrate H. Yuan, Z. Ma (University of Wisconsin), C. Ritz, D. Savage, M. Lagally (University of Wisconsin-Madison) and G. Celler (Soitec)
15:40 723 Threshold Voltage Instability of Top Gate Single-Crystalline Si Thin-film Transistors on Flexible Substrate Using SiO as Gate Dielectric H. Pang, H. Yuan, Z. Ma (University of Wisconsin), M. Lagally (University of Wisconsin-Madison) and G. Celler (Soitec)
16:00 Intermission (20 Minutes)
16:20 724 Heat Generation and Transport in SOI and GOI Devices E. Pop (Univ. Illinois Urbana-Champaign)
17:00 725 Electronic and Thermal Properties of Silicon Nanowires E. B. Ramayya (University of Wisconsin - Madison), D. Vasileska, S. Goodnick (Arizona State University, Fulton School of Engineering) and I. Knezevic (University of Wisconsin - Madison)
17:20 726 Analysis of PD SOI pMOSFET Device Performance Enhancement due to Direct-Tunneling Current in the Partial n+ Poly Gate G. Guegan (CEA/DRT-LETI), J. Pretet (STMicroelectronics), R. Gwoziecki (CEA/DRT-LETI), O. Gonnard, G. Gouget (STMicroelectronics), P. Touret, C. Raynaud and S. Deleonibus (CEA/DRT-LETI)
 

Southwest Hall, Lower Level

Poster Session

Co-Chairs: G. Celler, S. Cristoloveanu
TimeAbs#Title and Authors
o 727 Non-contact Photoelectric Method For Thin SOI Characterization E. Tsidilkovski and K. Steeples (QC Solutions)
o 728 Implant Metrology for Bonded SOI Wafers using a Surface Photo-voltage Technique A. F. Bertuch, W. Smith (QC Solutions Inc.), K. Steeples (QC Solutions), R. Standley, A. Stefanescu (MEMC Electronic Materials Inc.) and R. Johnson (Innovion)
o 729 Low Temperature Properties of Multi-Independent-Gate FET (MIGFET) operating in Single-Gate and Double-Gate modes K. Na (Kyungpook Natl. Unvi.), S. Eminente (ARCES), S. Cristoloveanu (IMEP-INP Grenoble), L. Mathew, A. Vandooren (Freescale Semiconductor Inc.), Y. Bae (Uiduk University) and J. Lee (Kyungpook National University)
o 730 Analysis of Trench Gate Power LDMOS Transistors in Thin SOI Technology I. Cortes, P. Fernández-Martinez, D. Flores, S. Hidalgo and J. Rebollo (Centro Nacional de Micorelectronica (CNM))
o 731 3D Nonequilibrium Greens Function Device Solver Applied to Modeling of FinFET Devices D. Vasileska (Arizona State University, Fulton School of Engineering), H. Khan and D. Mamaluy (ASU)
o 732 Simple Analytical Model to Study the ZTC Bias Point in FinFETs M. Bellodi (Centro Universitario da FEI), L. Camillo (Laboratório de Sistemas Integráveis da USP), J. A. Martino (FEI/USP), E. Simoen and C. Claeys (IMEC)
o 733 Temperature Influences on FinFETs with Undoped Body M. A. Pavanello (Centro Universitario da FEI), J. A. Martino (FEI/USP), E. Simoen (IMEC), R. Rooyackers, N. Collaert (IMEC, Belgium) and C. Claeys (IMEC)
o 734 Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures M. A. Pavanello (Centro Universitario da FEI), A. Cerdeira (CINVESTAV, Mexico), J. Raskin and D. Flandre (Universite catholique de Louvain, Belgium)
 

Wednesday, May 9, 2007

Stevens 5, Northwest Hall, Lower Level

Material Characterization

Co-Chairs: S. Bedell, W. Xiong
TimeAbs#Title and Authors
08:20 735 SOI Metrology and Characterization in Modern Wafer Production O. Kononchuk, F. Brunier and M. Kennard (SOITEC)
09:00 736 Investigation of Apertureless NSOM for Measurement of Stress in Strained Silicon R. Geer, C. McDonough and Y. Wang (SUNY)
09:40 Intermission (20 Minutes)
10:00 737 Effective Control of Strain in SOI by SiN Deposition D. Kosemura and A. Ogura (Meiji University)
10:20 738 Structural Properties of Tensile-Strained Si Layers Grown on Si1-xGex Virtual Substrates (x = 0.2, 0.3, 0.4 and 0.5) J. Hartmann (CEA-LETI, Minatec), D. Rouchon, P. Holliger (CEA-LETI), M. Mermoux (LEPMI / ENSEEG / INPG) and T. Billon (CEA-LETI)
10:40 739 X-Ray Absorption Spectroscopy Study of Biaxially Strained Si Nanomembranes C. Euaruksakul, Z. Li, D. Savage and M. Lagally (University of Wisconsin-Madison)
11:00 740 Comparison of Differenbt Etching Techniques in Order to Reveal Dislocations in Thick Ge Layers A. Abbadie (SOITEC, Bernin), J. Hartmann (CEA-LETI, Minatec) and C. Deguet (CEA-LETI)
11:20 741 Development of a Chromium-free Defect Etching Solution for Application on SOI J. Maehliss (JWG-University), A. Abbadie (SOITEC, Bernin) and B. Kolbesen (JWG-University, Frankfurt)
11:40 742 Mobility Characterization by Magnetoresistance in Ultra Thin SOI Ring-FETs S. Cristoloveanu (IMEP-INP Grenoble) and V. C. Turumella (University of Western Australia)
 

Technology and Materials

Co-Chairs: B.-Y. Nguyen, R. Geer
TimeAbs#Title and Authors
14:00 743 Strained Silicon Directly on Insulator (SSOI): Biaxial, Uniaxial, or Hybrid Strain? A. Thean (Freescale Semiconductor)
14:40 744 Hybrid orientation Si-Si interfaces by hydrophilic wafer bonding and high temperature oxide dissolution: wafer fabrication technique and device applications K. Saenger, J. de Souza, K. Fogel, J. Ott, A. Reznicek (T.J. Watson Research Center), H. Yin, C. Sung (IBM Semiconductor Research and Development Center) and D. Sadana (T.J. Watson Research Center)
15:20 745 Fabrication of SOI MOSFET by "Separation by Bonding Silicon Islands (SBSI)" Method K. Kanemoto, H. Oka, H. Hisamatsu, Y. Matsuzawa, Y. Kitano, T. Hara, M. Hoshina (Seiko Epson Corporation, Fujimi Plant), S. Ohmi (Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology) and J. Kato (Seiko Epson Corporation, Fujimi Plant)
15:40 746 Epitaxial Regrowth of Ge on SGOI and GeOI Substrates Obtained by Ge Condensation J. Damlencourt (CEA/LETI), Y. Campidelli (STMicroelectronics), M. Roure (CEA/LETI/DPTS), B. Vincent (CEA/LETI/D2NT/LFE), E. Martinez, F. Fillot, B. Arrazat (CEA/LETI/DPTS), T. Nguyen, S. Cristoloveanu (IMEP-INP Grenoble) and C. Laurent (CEA/LETI/D2NT/LNDE)
16:00 Intermission (20 Minutes)
16:20 747 Ordered Lattices of Quantum Dots on Ultrathin SOI Nanomembranes P. Evans, R. Clark, D. Detert (University of Wisconsin), M. Lagally (University of Wisconsin-Madison) and Z. Cai (Advanced Photon Source, Argonne National Laboratory)
16:40 748 LEGO Process for Mixed Power Applications: Fabrication at Low Cost of Localized Thick SOI Layers J. R. Dilhac (LAAS-CNRS), I. Bertrand (SOITEC), J. Dilhac (LAAS-CNRS), P. Renaud (Freescale Semiconductors), M. Bafleur and C. Ganibal (LAAS-CNRS)
17:00 749 A Novel Method to Fabricate Multiple-layer SOI -- Single-Crystal Si Nanomembrane Transfer and Stacking W. Peng, M. Roberts, E. Nordberg, F. Flack, P. Colavita, R. Hamers (University of Wisconsin Madison), D. Savage, M. Lagally (University of Wisconsin-Madison) and M. Eriksson (University of Wisconsin Madison)
17:20 750 Strained Silicon-On-Insulator - Fabrication and Characterization M. Reiche, C. Himcinschi, U. Gösele, S. Christiansen (MPI Halle), S. Mantl, D. Buca, Q. Zhao, S. Feste (FZ Jülich), R. Loo, D. Nguyen (IMEC Leuven), W. Buchholtz, A. Wei, M. Horstmann (AMD Dresden), D. Feijoo and P. Storck (Siltronic AG)
17:40 751 Advanced Heterostructure Si-InSb on Insulator Formed by Hydrogen Transfer of Bonded Si Layer and SiO2 Film V. P. Popov, I. Tyschenko and E. Cherkov (Instittute of Semiconductor Physics)
 

Thursday, May 10, 2007

Stevens 5, Northwest Hall, Lower Level

Computer Simulations

Co-Chairs: F.Gamiz, E. Pop
TimeAbs#Title and Authors
08:20 752 Atomic-Scale Simulations of Electron Mobilities in Ultrathin SOI MOSFETs S. T. Pantelides, G. Hadjisavvas, M. Evans, L. Tsetseris, M. Caussanel and R. Schrimpf (Vanderbilt University)
09:00 753 Electronic Transport in `Unconventional' SOI MOS Systems: Thin-Body and High-k Effects in Si, Ge, and III-V Layers M. V. Fischetti, S. Jin, S. Narayanan and T. O'Regan (University of Massachusetts, Amherst)
09:40 Intermission (20 Minutes)
10:00 754 Study of the Corner Effects on Pi-Gate SOI MOSFETs F. G. Ruiz, A. Godoy, F. Gamiz, C. Sampedro and L. Donetti (University of Granada)
10:20 755 Impact of Phonon-Limited Mobility Superiority in Double-Gate or Fin FET with a (111) Si and (001) Ge Surface Channel on Device Scaling T. Yamamura, S. Sato and Y. Omura (Kansai University)
10:40 756 Significance of Gate Underlap Architecture in FinFETs for Low-Voltage Analog/RF Applications A. Kranti and G. Armstrong (Queen's University Belfast)
11:00 757 Non-Vertical Sidewall Angle Influence on Triple-Gate FinFETs Corner Effects R. Giacomini and J. A. Martino (FEI/USP)
11:20 758 Improved Model to Determine the Generation Lifetime in Short Channel SOI nMOSFETs M. Galeti (University of Sao Paulo), J. A. Martino (FEI/USP), E. Simoen and C. Claeys (IMEC)
11:40 Symposium Concluding Remarks (10 Minutes)