212th ECS Meeting - Washington, DC

October 7 - October 12, 2007

PROGRAM INFORMATION
 

E9 - ULSI Process Integration 5

Electronics and Photonics
 

Monday, October 8, 2007

Georgetown Room West, Concourse Level

Keynotes and Opening Session

Co-Chair(s): C. Claeys and H. Iwai
TimeAbs#Title and Authors
14:00   1272   Current Status and Perspective of High-k Gate Stack Materials Engineering for Further Scaled CMOS A. Toriumi (The University of Tokyo)
14:40   1273   Emerging Research Nanoelectronic Devices: The Choice of Information Carrier V. Zhirnov and R. Cavin (Semiconductor Research Corporation)
15:20   1274   Analysis of Technology Variations in Advanced MOSFETS with the Surface-Potential-Based Compact Model HiSIM M. Miura-Mattausch, N. Sadachika, M. Miyake, A. Yumisaki and M. Miura-Mattausch (Hiroshima University)
16:00 Intermission (20 Minutes)
16:20   1275   Silicide and Germanide Technology for Contacts and Metal Gates in MOSFET Applications S. Zaima, O. Nakatsuka, H. Kondo, M. Sakashita (Nagoya University), A. Sakai (Osaka University) and M. Ogawa (Nagoya University)
16:50   1276   Characterization of Electronic Charged States of Si-Based Quantum Dots for Floating Gate Application S. Miyazaki, M. Ikeda and K. Makihara (Hiroshima University)
 

Tuesday, October 9, 2007

Georgetown Room West, Concourse Level

Strain Engineering and High Mobility substrates I

Co-Chair(s): S. Deleonibus and M. Tao
TimeAbs#Title and Authors
08:10   1277   Enhanced Channel Mobility Materials for MOSFETs on Si Substrates S. Banerjee, E. Tutuc (University of Texas), J. Donnelly (University of Texas-Austin) and D. Shahredji (University of Texas)
08:40   1278   Mobility-Enhanced Device Technologies Using SiGe/Ge MOS Channels S. Takagi (The University of Tokyo), T. Irisawa, T. Tezuka, T. Numata, N. Hirashita, K. Usuda and N. Sugiyama (MIRAI-ASET)
09:10   1279   Fabrication of SiGe Virtual Substrates by Ion Implantation Technique K. Sawano, Y. Shiraki (Musashi Institute of Technology) and K. Nakagawa (University of Yamanashi)
09:40 Intermission (20 Minutes)
 

Strain Engineering and High Mobility substrates II

Co-Chair(s): M. Tao and S. Deleonibus
TimeAbs#Title and Authors
10:00   1280   Strain Control of Si and Si1-xGex Layers in the Si/Si1-xGex/Si Heterostructures by Stripe-Shape Patterning for Future Si-Based Devices J. Murota (Res. Inst. Electr. Comm., Tohoku Univ.), J. Uhm (Res. Inst. Electr. Comm., Tohoku University) and M. Sakuraba (Tohoku University)
10:30   1281   Does Strain Engineering Impacts the Gate Stack Quality and Reliability? C. Claeys (IMEC), E. Simoen (IMEC, Belgium) and F. Crupi (Universtity of Calabria, Italy)
11:00   1282   High-k Gate Stack Formation on Strained SiGe Substrate for MOSFET Applications C. Zhu, M. Li, J. Huang and J. Fu (National University of Singapore)
11:30   1283   Fabrication of Hole Resonant Tunneling Diodes with Nanometer Order Heterostructures of Si/Strained Si1-xGex Epitaxially Grown on Si(100) M. Sakuraba (Tohoku University), R. Ito, T. Seo and J. Murota (Res. Inst. Electr. Comm., Tohoku Univ.)
 

Gate Dielectric and Workfunction Engineering

Co-Chair(s): J. Murota and J. J. Liou
TimeAbs#Title and Authors
14:00   1284   Breakdown Characteristics of High-k Gate Dielectrics with Metal Gates D. Misra (New Jersey Institute of Technology)
14:30   1285   A Cost-Effective CMOS Technology Utilizing Gate Work Function Control with Hafnium G. Tsutsui, H. Nakamura, T. Fukase and K. Imai (NEC Electronics)
15:00   1286   Nano-Scale Profile of the Dielectric Constant Near the Si/oxide Interface: A First-Principles Approach J. Nakamura, S. Wakui, S. Eguchi, R. Yanai and A. Natori (The University of Electro-Communications)
15:30   1287   Angle-Resolved Photoelectron Spectroscopy Study on Ultrathin Gate Dielectrics H. Nohira (Musashi Institute of Technology) and T. Hattori (New Industry Creation Hatchery Center, Tohoku University)
16:00 Intermission (20 Minutes)
 

Silicides and Metallization

Co-Chair(s): S. Zaima
TimeAbs#Title and Authors
16:20   1288   Improvement of Thermal Stability of Ni Silcide by Additive Metals with Specific Introduction Processes K. Tsutsui, K. Nagahiro, T. Shiozawa, P. Ahmet, K. Kakushima and H. Iwai (Tokyo Institute of Technology)
16:50   1289   In Situ Dry Chemical Clean to Improve NiSi and Ni(Pt)Si Integration B. S. Wood, J. Lei, S. Phan, B. Ninan, K. Lavu (Applied Materials), M. Smayling (Tela Innovations), C. Kao and S. Gandikota (Applied Materials)
17:10   1290   Salicide Integration Optimization for Improved Yield J. M. Towner and J. J. Naughton (AMI Semiconductor)
 

Exhibit Hall, Concourse Level

Poster Session

TimeAbs#Title and Authors
o   1291   Effect of Agglomerated Cu Seed Layer on Cu Removal Rate during Chemical Mechanical Planarization J. Lin, C. Wan, Y. Wang (National Tsing-Hua University), H. Feng and M. Cheng (TSMC)
o   1292   Effect of Fe/Si Ratio on Epitaxial Growth of Fe3Si on Ge Substrate M. Kumano, Y. Ando, K. Ueda, T. Sadoh (Kyushu University), K. Narumi (Japan Atomic Energy Agency), Y. Maeda (Kyoto University) and M. Miyao (Kyushu University)
o   1293   Formation of Fe3Si/Ge/Fe3Si Multi-layer by Double Heteroepitaxy on High Quality Fe3Si/Ge Substrate for Spintronic Application K. Ueda, Y. Ando, M. Kumano, T. Sadoh (Kyushu University), Y. Maeda (Kyoto University) and M. Miyao (Kyushu University)
o   1294   Comparative Study of Al-Induced Crystallization for Poly-Si and Ge on Insulating Film Y. Tsumura, I. Nakao, H. Kanno, A. Kenjo, T. Sadoh and M. Miyao (Kyushu University)
o   1295   Acceleration Effect of CuCN in Ag Electrodeposition for Metal Interconnection S. Cho, J. Lee (Seoul National University), S. Kim (Korea Institute of Science and Technology) and J. Kim (Seoul National University)
 

Wednesday, October 10, 2007

Georgetown Room West, Concourse Level

FEOL and BEOL Processing Issues

TimeAbs#Title and Authors
08:00   1296   Novel SONOS and Floating-Gate Flash Memory Cell Structures for High Density and High Reliability Applications R. Huang (Institute of Microelectronics)
08:30   1297   Integration Issues in Metallic Source/Drain Nanoscale CMOS M. Tao (University of Texas at Arlington)
09:00   1298   Leveling Characteristics of Wide Features J. Sukamto, C. Veazey, E. Webb and J. Reid (Novellus Systems Inc.)
09:20   1299   Composite Shallow Trench Isolation Using Silicon Nitride and Doped Polysilicon for Ultra-Low Power CMOS A. G. Gokirmak and H. Silva (University of Connecticut)
09:40 Intermission (20 Minutes)
 
TimeAbs#Title and Authors
10:00   1300   Integration Solutions in 65nm BEOL Defect Reduction and Manufacturability H. Hichri, S. Lane, M. Angyal, J. S. Oakley, C. Bunke and D. Watts (IBM)
10:30   1301   High-Performance CMP Slurry with CeO2/Resin Abrasive for STI Formation Y. Matsui, Y. Tateyama, K. Iwade, T. Nishioka and H. Yano (Semiconductor Company, Toshiba Corporation)
10:50   1302   Selective Formation of Micropads for 3D Interconnect Applications V. Mathew, R. Chatterjee, S. Garcia, E. Acosta and R. Jones (Freescale Semiconductor,Inc.)
11:10   1303   Pretreatment of Ru Liner for Direct Cu Plating I. Shao, B. Baker-O'Neal, J. Kelly, K. Kwietniak and P. Vereecken (IBM Corp.)
11:30   1304   Effects of Liner Metal and CMP Slurry Oxidizer on Copper Galvanic Corrosion S. Shima, A. Fukunaga and M. Tsujimura (Ebara Corporation)
11:50   1305   Increase of Carbon Substitutionality and Silicon Strain by Molecular Ion Implantation A. Li-Fatou, A. Jain (Texas Instruments, Inc.), W. Krull (SemEquip Inc.), M. Ameen, M. Harris (Axcelis) and D. Jacobson (SemEquip)
 

Processing Integration

Co-Chair(s): H. Ru and H. Hichri
TimeAbs#Title and Authors
14:00   1306   Integration Challenges and Opportunities for Nanometer Scale CMOSFET with Metal/High-k Gate Stack S. Song, M. Hussain, J. Barnett, C. S. Park, C. Park, P. Kirsch and B. Lee (Sematech)
14:30   1307   Critical Components of FinFet Integration: Examining the Density Trade-off and Process Integration for FinFET Implementation R. Harris, M. Hussain, C. Smith, J. Yang, J. Barnett, B. Sassman, S. Song, B. Lee, H. Tseng and R. Jammy (Sematech)
15:00   1308   Advanced DG-MOSFETs Process Technologies E. Suzuki, Y. Liu, K. Endo, T. Matsukawa, M. Masahara, K. Sakamoto and S. O'uchi (National Institute of Advanced Industrial Science and Technology (AIST))
15:30   1309   Performance Boost Using a New Device Structure Design for SOI MOSFETs Beyond 25nm Node W. Cheng, A. Teramoto and T. Ohmi (Tohoku University)
15:50 Intermission (20 Minutes)
16:10   1310   Challenges and Issues in 65nm CMOS Logic Technology W. Lee (IBM)
16:40   1311   Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond D. Park (IBM T.J.Watson Research Center)
17:10   1312   CMOS Scaling Beyond High-k and Metal Gates P. Majhi, P. Kalra, J. Oh, R. Harris, H. Tseng and R. Jammy (Sematech)
17:40   1313   Formation of Silicided Hyper-Shallow p+/n- Junctions by Pulsed Laser Annealing K. L. Pey (Nanyang Technological University), K. Ong, P. Lee, Y. Setiawan, X. Wang, A. Wee and G. Lim (Nanyang Technical University)
 

Thursday, October 11, 2007

Georgetown Room West, Concourse Level

Alternative and Emerging Materials and Device

Co-Chair(s): V. Shirnov and M. Lemme
TimeAbs#Title and Authors
08:00   1314   Transport in Ultrathin SOI MOSFETs and Silicon Nanowire Transistors T. Hiramoto (University of Tokyo)
08:30   1315   Low-Temperature Epitaxial Grwoth of [Fe3Si/SiGe]n (n=1-2) Multi-Layered Structures for Spintronics Application T. Sadoh, K. Ueda, Y. Ando, M. Kumano (Kyushu University), K. Narumi (Japan Atomic Energy Agency), Y. Maeda (Kyoto University) and M. Miyao (Kyushu University)
09:00   1316   Towards Graphene Field Effect Transistors M. C. Lemme, T. Echtermeyer, M. Baus and H. Kurz (AMO GmbH)
09:30   1317   Surface Energy Characterization of Partially Cured Benzocyclobutene for 3D Interconnect Applications J. J. McMahon, R. Gutmann and J. Lu (Rensselaer Polytechnic Institute)
09:50 Intermission (20 Minutes)
10:10   1318   Integration Issues and Progress for High Volume Carbon Nanotube Nanoelectronics R. Carter (Advanced Micro Devices)
10:40   1319   MMICs Using SiGe BiCMOS for Ubiquitous Wireless Network T. Masuda, N. Shiramizu and K. Washio (Hitachi, Central Research Laboratory)
11:10   1320   High-Frequency Device Options for Systems-on-Chip F. Schwierz (Technische Universitaet Ilmenau)
11:40   1321   High Volt Mixed Signal Integration Challenges M. Tyler and J. J. Naughton (AMI Semiconductor)
12:00   1322   Advantages of Nano-Grating Si Substrates in CMOS-FET Characteristics X. Zhu, S. Kuroki, K. Kotani and T. Ito (Tohoku University)