Co-Chairs: C.L. Claeys and G. Bronner
| Time | Abs# | Title | View |
|---|---|---|---|
| 10:00 | 395 | ULSI Process Integration for 2005 and Beyond - H. Iwai and S.-I. Ohmi (Tokyo Institute of Technology) | |
| 10:40 | 396 | Process Technologies for Sub-100-nm CMOS Devices - H. Wakabayashi (Microsystems Technology Laboratories, Massachusetts Institute of Technology), M. Ueki, K. Uejima, T. Fukai, M. Togo, T. Yamamoto, K. Takeuchi, T. Mogami, M. Narihiro, and Y. Ochiai (NEC Corporation) | |
| 11:10 | 397 | Directions of Future Memory Technology - J.W. Park (Samsung Electronics Co.) |
Co-Chairs: R. Reif and H. Iwai
| Time | Abs# | Title | View |
|---|---|---|---|
| 2:00 | 398 | Future Prospects for sub. 100nm Lithography - A. Ishitani (Association of Super-advanced Electronics Technologies) | |
| 2:30 | 399 | The Scaling Issues of COB Stack DRAM Cell Technology and Its Directions for Beyond 100 nm Technology Node - K. Kim (Samsung Electronics Co., LTD) | |
| 3:00 | 400 | Process Integration of In-situ Doped PolySilicon for ULSI Technologies - E.-X. Ping (Micron Technology) | |
| 3:30 | 401 | Quantum Mechanical Narrow Channel Effect in Nano-Scale MOSFETs - T. Hiramoto and H. Majima (University of Tokyo) | |
| 4:00 | Ten-Minute Intermission | ||
| 4:10 | 402 | Review of the FeRAM Process Integration: Issues and Problems - N.S. Kang (Hyundai Electronics Inc.) | |
| 4:40 | 403 | Copper and Low-k Dielectric Integration Challenges - J.G. Ryan, M.B. Anand, G. Biery, C. Davis, P. Duncombe, D. Edelstein, S. Gates, S. Greco, J. Hedrick, P. Jones, M. Lane, E. Levine, V. McGahay, C. Narayan, S. Nitta, T. Shaw, T. Spooner, and R.D. Goldblatt (IBM Corporation) | |
| 5:10 | 404 | Three-Dimensional Integration with Copper Wafer Bonding - R. Reif and A. Fan (Massachusetts Institute of Technology) | |
| 5:40 | 405 | Ultra-Shallow Junction Formation by Atomic Layer Doping - M. Koyanagi (Tohoku University) |
Co-Chairs: J. Murota and A. Ourmazd
| Time | Abs# | Title | View |
|---|---|---|---|
| 8:00 | 406 | Silicon Germanium Trends on Process Integration - E. Kasper (University of Stuttgart) | |
| 8:40 | 407 | SiGe HBT/CMOS Technology for RF and High-Speed Digital Applications - K. Washio (Hitachi Ltd.) | |
| 9:10 | 408 | Modular, High-Performance BiCMOS by Integration of SiGe:C HBTs - D. Knoll, B. Heinemann, K.-E. Ehwald, H. Rücker, B. Tillack, and H.-J. Osten (IHP) | |
| 9:40 | 409 | Fabrication of High Quality MOS Structures with SiGe Buried Channels for CMOS Applications - S. Kar (Indian Institute of Technology, Kanpur) and P. Zaumseil (Institute of Semiconductor Physics) | |
| 10:00 | Twenty-Minute Intermission | ||
| 10:20 | 410 | Threshold Voltage Stability of P-Channel MOSFETs With Heavily Boron Doped SiGeC Gate Layers - E. Stewart, M. Carroll, and J.C. Sturm (Princeton University) | |
| 10:40 | 411 | Integration Issues in Silicon-Based ICs for Telecommunication Applications - G. Freeman (IBM) | |
| 11:10 | 412 | Low Frequency Noise in Si1-xGex-Channel pMOSFETs - T. Tsuchiya (Shimane University), T. Matsuura, and J. Murota (Tohoku University) | |
| 11:30 | 413 | Parasitic Channel in SiGe Heterojunction p-MOSFET's - Y. Hara, A. Inoue, T. Takagi, Y. Kanzawa, and M. Kubo (Matsushita Electric Industrial Co.,Ltd.) |
Co-Chairs: K. Saraswat and J. Borland
| Time | Abs# | Title | View |
|---|---|---|---|
| 1:50 | 414 | The Gate Stack / Shallow Junction Challenge for Sub-100 nm Technology Generations: Gate Stack Emphasis - H.R. Huff, G.A. Brown, and L.A. Larson (International SEMATECH, Inc.) | |
| 2:30 | 415 | Process Integration for DRAM Cell Transistor Optimization - S. Lee, S. Park, and I. Kim (Hyundai Electronics Industries) | |
| 3:00 | 416 | Vertical Pass Transistor Integration for Future DRAM - R. Divakaruni and G. Bronner (DRAM Development Alliance of IBM - Infineon) | |
| 3:30 | Ten-Minute Intermission | ||
| 3:40 | 417 | Improved Device Scaling & Process Simplification Through Advanced Ion Implantation Techniques - J. Borland (Varian Semiconductor Equipment Associates) | |
| 4:10 | 418 | Transistor Design Methodology For Low Power CMOS Microprocessors - J. Buller, J. Cheek, and D. Wristers (Advanced Micro Devices) | |
| 4:30 | 419 | L-Shape Spacer Architecture for Low Cost, High Performance CMOS - E. Augendre, C. Perello, E. Vandamme, S. Pochet, R. Rooyackers, S. Beckx, M. De Potter, A. Lauwers, and G. Badenes (IMEC vzw) | |
| 4:50 | 420 | Impact of Indium and Boron interaction on Short Channel and Reverse Short Channel Effects for nMOSFETs - S.Y. Ong, E.F. Chor (National University of Singapore), J. Lee, Y.K. Leung, A. See, and L. Chan (Chartered Semiconductor Manufacturing Ltd) | |
| 5:10 | 421 | Enhanced Short-Channel Effects of sub-50nm Gate Length MOSFETs with High-k Gate Insulator Films - R. Fujimura, M. Takeda, K. Sato, S.-I. Ohmi, H. Ishiwara, and H. Iwai (Tokyo Institute of Technology) | |
| 5:30 | 422 | Side-Wall Protection by B in P-Doped Polysilicon in Gate Etching - T. Seino, A. Fukuchi, T. Matsuura, and J. Murota (Tohoku University) |
Co-Chairs: F. Gonzalez and S. Koveshnikov
| Time | Abs# | Title | View |
|---|---|---|---|
| 10:00 | 423 | Impact of Metallic Impurities on Integrity of Ultra-Thin Gate Oxides and Gettering in Advanced Si Wafers - S. Koveshnikov, D. Beauchaine (SEH America, Inc.), and F. Gonzalez (Micron Technology, Inc.) | |
| 10:30 | 424 | Thermally Induced Dislocation and Slip Defects in Silicon - C.-R. Cho, Y.S. Kim, J.K. Lee, S.W. Ko, K.Y. Noh, D.J. Choi, D.H. Kim, C.B. Son, D.H. Cho, J.J. Choi, and D.J. Kim (Fairchild Korea Semiconductor) | |
| 10:50 | 425 | Process-Induced Defects and Diode leakage in ULSI FEOL integration - K. Parekh, C. Mouli, M. Hermes, and F. Gonzalez (Micron Technology, Inc.) | |
| 11:20 | 426 | Reduction of Substrate Leakage Current by Minimizing Trench-Isolation-Induced Stress - H. Miura, N. Ishitsuka (Hitachi, Ltd.), N. Suzuki, K. Ohyu, and S. Ikeda (Semiconductor Group) | |
| 11:40 | 427 | Plasma-Induced Damage Reduction by Spin-on Low-k Dielectrics Process - N. Matsunaga, H. Yoshinari, N. Yamada, and H. Shibata (Toshiba Corporation) |
Co-Chairs: X.R. Ping and S. Saito
| Time | Abs# | Title | View |
|---|---|---|---|
| 2:00 | 428 | DIELECTRIC SCIENCE AND TECHNOLOGY DIVISION T.D. CALLINAN AWARD ADDRESS-Evolution of the Metallization Concepts for Applications in the Integrated Circuits - S.P. Murarka (Rensselaer Polytechnic Institute) | |
| 2:30 | 429 | Silicon-Based Technologies for Wireless - A. Ourmazd (IHP) | |
| 3:10 | 430 | Practical Roadmap and Approach of Multi-level Interconnect Technology for Realizing Over-GHz-Age System-On-Chip - H. Shibata (Toshiba Corporation) | |
| 3:40 | 431 | Electromigration Failure Modes in Cu Metallization - M. Gall, C. Capasso, H. Kawasaki, S. Thrasher (Motorola), L. Zhao (Advanced Micro Devices), and M. Herrick (Motorola) | |
| 4:10 | 432 | High Density 0.16um Merged DRAM/Logic Technology for System-on-a-Chip - H. Tanaka, J. Ida, M. Takeda, H. Shinohara, E. Seo, A. Kita, and F. Yokoyama (Oki Electric Industry Co., Ltd.) | |
| 4:30 | Ten-Minute Intermission | ||
| 4:40 | 433 | Back-end Process Integration for Logic LSI - S. Saito (NEC Electron Devices) | |
| 5:10 | 434 | Low Resistivity Contact Materials for ULSI Applications and Matal/Semiconductor Interfaces - S. Zaima and Y. Yasua (Nagoya University) | |
| 5:40 | 435 | A Manufacturing Process Technology for 0.16Ym Embedded DRAM with High Logic Speed and Small DRAM Cell - J.H. Lee, T.S. Oh, Y.S. Jeong, J.B. Kim, S.Y. Chi, E.M. Huh, S.D. Jeon, M.G. Jang, and D.H. Lee (Hyundai Electronics Industries Co., Ltd.) |
Co-Chairs: D.K. Sadana and J. Woo
| Time | Abs# | Title | View |
|---|---|---|---|
| 8:30 | 436 | MOS Transistor Scaling Challenges - M. Bohr (Intel Corp) | |
| 9:00 | 437 | Embedded DRAM and SOI Integration Issues - S.S.K. Iyer (IBM Microelectronics Division), D.K. Sadana (IBM Research Division), H.L. Ho, and S.S. Iyer (IBM Microelectronics Division) | |
| 9:30 | 438 | SOI for Logic and Memory Applications - D.K. Sadana (T.J. Watson Research Center, IBM) | |
| 10:00 | Thirty-Minute Intermission | ||
| 10:30 | 439 | Sub-25nm Device Challenges - J. Woo (UCLA) | |
| 11:00 | 440 | Some Manufacturing Techniques for Thin Film SOI - A. Wittkower (Soitec USA, Inc.), C. Maleville, T. Barge, and A.-J. Auberton-Herve (Soitec S.A.) | |
| 11:30 | 441 | Technologies for Large-Area Electronics on Deformable Substrates - J.C. Sturm, P.I. Hsu, M. Huang, H. Gleskova, M. Wu, R. Bhattacharya, S. Miller, A. Darhuber, S. Wagner, Z. Suo, and S. Troian (Princeton University) |
Co-Chairs: D.L. Kwong and E. Augendre
| Time | Abs# | Title | View |
|---|---|---|---|
| 2:00 | 442 | Interface Technology for Advanced Gate Dielectrics - M. Niwa, Y. Harada, K. Eriguchi (Matsushita Electronics Corporation), and D.-L. Kwong (The University of Texas at Austin) | |
| 2:30 | 443 | Characterization of Traps in ONO Films for MONOS Nonvolatile Memory - H. Aozasa, I. Fujiwara, K. Nomoto, S. Tanaka, and T. Kobayashi (Sony Corporation) | |
| 2:50 | 444 | Optimisation of Active Area Edge Protection in Shallow Trench Isolation - E. Augendre, R. Rooyackers, S. Pochet, L. Grau, E. Sleeckx, E. Vandamme, and G. Badenes (IMEC vzw) | |
| 3:10 | 445 | A Study on the Microstructures and Electrical Properties of ZrO2 Thin Films - S.-W. Nam, J.-H. Yoo, H.-Y. Kim, D.-H. Ko (Yonsei University), and C.-W. Yang (Sungkyunkwan University) | |
| 3:30 | 446 | Diffusion Barrier Performance of CVD-Grown TiSiN Films - D. Anjum, S. Oktyabrsky, E. Eisenbraun, and A. Kaloyeros (University at Albany-State University of New York) | |
| 3:50 | Twenty-Minute Intermission | ||
| 4:10 | 447 | Ni Salicide Technology for Deep Sub-Quarter Micron Transistor - C.-J. Choi, J.-H. Ku, S. Choi, K. Fujihara, H.-K. Kang, J.-T. Moon (Samsung Electronics Co., Ltd.), H.-J. Choi, and D.-H. Ko (Yonsei University) | |
| 4:30 | 448 | Formation and Properties of Co-Silicide by Using Co1-XTaX Alloy - M.-J. Kim, D.-H. Ko, D.-H. Lee (Yonsei University), J.-H. Ku, S. Choi, K. Fujihara, H.-K. Kang (Division Samsung Electronics Co.), and H.-J. Lee (Stanford University) | |
| 4:50 | 449 | The Physical and Electrical Properties of Poly Si1-x Gex as a Gate Electrode Materials - S.-K. Kang, D.-H. Ko (Yonsei University), T.-H. Ahn, M.-S. Joo, I.-S. Yeo (Hyundai Electronics Industries Co. Ltd.), S.-J. Whoang, D.-Y. Yang, C.-J. Whang (Ju-Sung Co. Ltd.), and H.-J. Lee (Stanford University) | |
| 5:10 | 450 | A Study of the Solid Phase Reaction and Thermal Stability in the Ni-S1-x System Using Rapid Thermal Annealing (RTA) Process - H.-J. Choi, D.-H. Ko, H.-Y. Kim, D.-H. Lee (Yonsei University), J.-H. Ku, C.-J. Choi, S. Choi, K. Fujihara, H.K. Kang (Samsung Electronics Co.), C.-W. Yang, and M.-H. Yang (Sungkyunkwan University) |