199th Meeting - Washington, DC

March 25-30, 2001


M3 - Second International Symposium on ULSI Process Integration

Electronics Division

Monday, March 26, 2001

Central Salon, Ballroom Level

Full Process Integration and Device Scaling

Co-Chairs: C.L. Claeys and G. Bronner

10:00395 ULSI Process Integration for 2005 and Beyond - H. Iwai and S.-I. Ohmi (Tokyo Institute of Technology) PDF
10:40396 Process Technologies for Sub-100-nm CMOS Devices - H. Wakabayashi (Microsystems Technology Laboratories, Massachusetts Institute of Technology), M. Ueki, K. Uejima, T. Fukai, M. Togo, T. Yamamoto, K. Takeuchi, T. Mogami, M. Narihiro, and Y. Ochiai (NEC Corporation) PDF
11:10397 Directions of Future Memory Technology - J.W. Park (Samsung Electronics Co.) PDF

Full Process Integration and Device Performance

Co-Chairs: R. Reif and H. Iwai

2:00398 Future Prospects for sub. 100nm Lithography - A. Ishitani (Association of Super-advanced Electronics Technologies) PDF
2:30399 The Scaling Issues of COB Stack DRAM Cell Technology and Its Directions for Beyond 100 nm Technology Node - K. Kim (Samsung Electronics Co., LTD) PDF
3:00400 Process Integration of In-situ Doped PolySilicon for ULSI Technologies - E.-X. Ping (Micron Technology) PDF
3:30401 Quantum Mechanical Narrow Channel Effect in Nano-Scale MOSFETs - T. Hiramoto and H. Majima (University of Tokyo) PDF
4:00 Ten-Minute Intermission
4:10402 Review of the FeRAM Process Integration: Issues and Problems - N.S. Kang (Hyundai Electronics Inc.) PDF
4:40403 Copper and Low-k Dielectric Integration Challenges - J.G. Ryan, M.B. Anand, G. Biery, C. Davis, P. Duncombe, D. Edelstein, S. Gates, S. Greco, J. Hedrick, P. Jones, M. Lane, E. Levine, V. McGahay, C. Narayan, S. Nitta, T. Shaw, T. Spooner, and R.D. Goldblatt (IBM Corporation) PDF
5:10404 Three-Dimensional Integration with Copper Wafer Bonding - R. Reif and A. Fan (Massachusetts Institute of Technology) PDF
5:40405 Ultra-Shallow Junction Formation by Atomic Layer Doping - M. Koyanagi (Tohoku University) PDF

Tuesday, March 27, 2001

Process Integration of SiGe Technologies

Co-Chairs: J. Murota and A. Ourmazd

8:00406 Silicon Germanium Trends on Process Integration - E. Kasper (University of Stuttgart) PDF
8:40407 SiGe HBT/CMOS Technology for RF and High-Speed Digital Applications - K. Washio (Hitachi Ltd.) PDF
9:10408 Modular, High-Performance BiCMOS by Integration of SiGe:C HBTs - D. Knoll, B. Heinemann, K.-E. Ehwald, H. Rücker, B. Tillack, and H.-J. Osten (IHP) PDF
9:40409 Fabrication of High Quality MOS Structures with SiGe Buried Channels for CMOS Applications - S. Kar (Indian Institute of Technology, Kanpur) and P. Zaumseil (Institute of Semiconductor Physics) PDF
10:00 Twenty-Minute Intermission
10:20410 Threshold Voltage Stability of P-Channel MOSFETs With Heavily Boron Doped SiGeC Gate Layers - E. Stewart, M. Carroll, and J.C. Sturm (Princeton University) PDF
10:40411 Integration Issues in Silicon-Based ICs for Telecommunication Applications - G. Freeman (IBM) PDF
11:10412 Low Frequency Noise in Si1-xGex-Channel pMOSFETs - T. Tsuchiya (Shimane University), T. Matsuura, and J. Murota (Tohoku University) PDF
11:30413 Parasitic Channel in SiGe Heterojunction p-MOSFET's - Y. Hara, A. Inoue, T. Takagi, Y. Kanzawa, and M. Kubo (Matsushita Electric Industrial Co.,Ltd.) PDF

FEOL Process Integration of Transistor Devices

Co-Chairs: K. Saraswat and J. Borland

1:50414 The Gate Stack / Shallow Junction Challenge for Sub-100 nm Technology Generations: Gate Stack Emphasis - H.R. Huff, G.A. Brown, and L.A. Larson (International SEMATECH, Inc.) PDF
2:30415 Process Integration for DRAM Cell Transistor Optimization - S. Lee, S. Park, and I. Kim (Hyundai Electronics Industries) PDF
3:00416 Vertical Pass Transistor Integration for Future DRAM - R. Divakaruni and G. Bronner (DRAM Development Alliance of IBM - Infineon) PDF
3:30 Ten-Minute Intermission
3:40417 Improved Device Scaling & Process Simplification Through Advanced Ion Implantation Techniques - J. Borland (Varian Semiconductor Equipment Associates) PDF
4:10418 Transistor Design Methodology For Low Power CMOS Microprocessors - J. Buller, J. Cheek, and D. Wristers (Advanced Micro Devices) PDF
4:30419 L-Shape Spacer Architecture for Low Cost, High Performance CMOS - E. Augendre, C. Perello, E. Vandamme, S. Pochet, R. Rooyackers, S. Beckx, M. De Potter, A. Lauwers, and G. Badenes (IMEC vzw) PDF
4:50420 Impact of Indium and Boron interaction on Short Channel and Reverse Short Channel Effects for nMOSFETs - S.Y. Ong, E.F. Chor (National University of Singapore), J. Lee, Y.K. Leung, A. See, and L. Chan (Chartered Semiconductor Manufacturing Ltd) PDF
5:10421 Enhanced Short-Channel Effects of sub-50nm Gate Length MOSFETs with High-k Gate Insulator Films - R. Fujimura, M. Takeda, K. Sato, S.-I. Ohmi, H. Ishiwara, and H. Iwai (Tokyo Institute of Technology) PDF
5:30422 Side-Wall Protection by B in P-Doped Polysilicon in Gate Etching - T. Seino, A. Fukuchi, T. Matsuura, and J. Murota (Tohoku University) PDF

Wednesday, March 28, 2001

Process Integration and Defect Interactions

Co-Chairs: F. Gonzalez and S. Koveshnikov

10:00423 Impact of Metallic Impurities on Integrity of Ultra-Thin Gate Oxides and Gettering in Advanced Si Wafers - S. Koveshnikov, D. Beauchaine (SEH America, Inc.), and F. Gonzalez (Micron Technology, Inc.) PDF
10:30424 Thermally Induced Dislocation and Slip Defects in Silicon - C.-R. Cho, Y.S. Kim, J.K. Lee, S.W. Ko, K.Y. Noh, D.J. Choi, D.H. Kim, C.B. Son, D.H. Cho, J.J. Choi, and D.J. Kim (Fairchild Korea Semiconductor) PDF
10:50425 Process-Induced Defects and Diode leakage in ULSI FEOL integration - K. Parekh, C. Mouli, M. Hermes, and F. Gonzalez (Micron Technology, Inc.) PDF
11:20426 Reduction of Substrate Leakage Current by Minimizing Trench-Isolation-Induced Stress - H. Miura, N. Ishitsuka (Hitachi, Ltd.), N. Suzuki, K. Ohyu, and S. Ikeda (Semiconductor Group) PDF
11:40427 Plasma-Induced Damage Reduction by Spin-on Low-k Dielectrics Process - N. Matsunaga, H. Yoshinari, N. Yamada, and H. Shibata (Toshiba Corporation) PDF

Process Integration in Integrated Circuit Applications

Co-Chairs: X.R. Ping and S. Saito

2:00428 DIELECTRIC SCIENCE AND TECHNOLOGY DIVISION T.D. CALLINAN AWARD ADDRESS-Evolution of the Metallization Concepts for Applications in the Integrated Circuits - S.P. Murarka (Rensselaer Polytechnic Institute) PDF
2:30429 Silicon-Based Technologies for Wireless - A. Ourmazd (IHP) PDF
3:10430 Practical Roadmap and Approach of Multi-level Interconnect Technology for Realizing Over-GHz-Age System-On-Chip - H. Shibata (Toshiba Corporation) PDF
3:40431 Electromigration Failure Modes in Cu Metallization - M. Gall, C. Capasso, H. Kawasaki, S. Thrasher (Motorola), L. Zhao (Advanced Micro Devices), and M. Herrick (Motorola) PDF
4:10432 High Density 0.16um Merged DRAM/Logic Technology for System-on-a-Chip - H. Tanaka, J. Ida, M. Takeda, H. Shinohara, E. Seo, A. Kita, and F. Yokoyama (Oki Electric Industry Co., Ltd.) PDF
4:30 Ten-Minute Intermission
4:40433 Back-end Process Integration for Logic LSI - S. Saito (NEC Electron Devices) PDF
5:10434 Low Resistivity Contact Materials for ULSI Applications and Matal/Semiconductor Interfaces - S. Zaima and Y. Yasua (Nagoya University) PDF
5:40435 A Manufacturing Process Technology for 0.16ƒYm Embedded DRAM with High Logic Speed and Small DRAM Cell - J.H. Lee, T.S. Oh, Y.S. Jeong, J.B. Kim, S.Y. Chi, E.M. Huh, S.D. Jeon, M.G. Jang, and D.H. Lee (Hyundai Electronics Industries Co., Ltd.) PDF

Thursday, March 29, 2001

Substrate Integration

Co-Chairs: D.K. Sadana and J. Woo

8:30436 MOS Transistor Scaling Challenges - M. Bohr (Intel Corp) PDF
9:00437 Embedded DRAM and SOI Integration Issues - S.S.K. Iyer (IBM Microelectronics Division), D.K. Sadana (IBM Research Division), H.L. Ho, and S.S. Iyer (IBM Microelectronics Division) PDF
9:30438 SOI for Logic and Memory Applications - D.K. Sadana (T.J. Watson Research Center, IBM) PDF
10:00 Thirty-Minute Intermission
10:30439 Sub-25nm Device Challenges - J. Woo (UCLA) PDF
11:00440 Some Manufacturing Techniques for Thin Film SOI - A. Wittkower (Soitec USA, Inc.), C. Maleville, T. Barge, and A.-J. Auberton-Herve (Soitec S.A.) PDF
11:30441 Technologies for Large-Area Electronics on Deformable Substrates - J.C. Sturm, P.I. Hsu, M. Huang, H. Gleskova, M. Wu, R. Bhattacharya, S. Miller, A. Darhuber, S. Wagner, Z. Suo, and S. Troian (Princeton University) PDF

FEOL Process Integration and Unit Processes

Co-Chairs: D.L. Kwong and E. Augendre

2:00442 Interface Technology for Advanced Gate Dielectrics - M. Niwa, Y. Harada, K. Eriguchi (Matsushita Electronics Corporation), and D.-L. Kwong (The University of Texas at Austin) PDF
2:30443 Characterization of Traps in ONO Films for MONOS Nonvolatile Memory - H. Aozasa, I. Fujiwara, K. Nomoto, S. Tanaka, and T. Kobayashi (Sony Corporation) PDF
2:50444 Optimisation of Active Area Edge Protection in Shallow Trench Isolation - E. Augendre, R. Rooyackers, S. Pochet, L. Grau, E. Sleeckx, E. Vandamme, and G. Badenes (IMEC vzw) PDF
3:10445 A Study on the Microstructures and Electrical Properties of ZrO2 Thin Films - S.-W. Nam, J.-H. Yoo, H.-Y. Kim, D.-H. Ko (Yonsei University), and C.-W. Yang (Sungkyunkwan University) PDF
3:30446 Diffusion Barrier Performance of CVD-Grown TiSiN Films - D. Anjum, S. Oktyabrsky, E. Eisenbraun, and A. Kaloyeros (University at Albany-State University of New York) PDF
3:50 Twenty-Minute Intermission
4:10447 Ni Salicide Technology for Deep Sub-Quarter Micron Transistor - C.-J. Choi, J.-H. Ku, S. Choi, K. Fujihara, H.-K. Kang, J.-T. Moon (Samsung Electronics Co., Ltd.), H.-J. Choi, and D.-H. Ko (Yonsei University) PDF
4:30448 Formation and Properties of Co-Silicide by Using Co1-XTaX Alloy - M.-J. Kim, D.-H. Ko, D.-H. Lee (Yonsei University), J.-H. Ku, S. Choi, K. Fujihara, H.-K. Kang (Division Samsung Electronics Co.), and H.-J. Lee (Stanford University) PDF
4:50449 The Physical and Electrical Properties of Poly Si1-x Gex as a Gate Electrode Materials - S.-K. Kang, D.-H. Ko (Yonsei University), T.-H. Ahn, M.-S. Joo, I.-S. Yeo (Hyundai Electronics Industries Co. Ltd.), S.-J. Whoang, D.-Y. Yang, C.-J. Whang (Ju-Sung Co. Ltd.), and H.-J. Lee (Stanford University) PDF
5:10450 A Study of the Solid Phase Reaction and Thermal Stability in the Ni-S1-x System Using Rapid Thermal Annealing (RTA) Process - H.-J. Choi, D.-H. Ko, H.-Y. Kim, D.-H. Lee (Yonsei University), J.-H. Ku, C.-J. Choi, S. Choi, K. Fujihara, H.K. Kang (Samsung Electronics Co.), C.-W. Yang, and M.-H. Yang (Sungkyunkwan University) PDF