199th Meeting - Washington, DC

March 25-30, 2001

PROGRAM INFORMATION

M5 - Tenth International Symposium on Silicon-on-Insulator Technology and Devices

Electronics Division

Monday, March 26, 2001

South Salon, Ballroom Level

Ultimate SOI Devices

Co-Chairs: S. Cristoloveanu and Y. Kado

TimeAbs#TitleView
10:15 Opening Remarks
10:30470 Ultimate SOI Transistors - Y. Taur (IBM TJ Watson Research Center) PDF
11:00471 Silicon on Nothing (SON) Fabrication, Material and Devices - T. Skotnicki (ST Microelectronics) PDF
11:30472 Single Electron Transistors and Other Nanodevices on SOI - T. Hiramoto, N. Takahashi, H. Ishikuro, and M. Saitoh (University of Tokyo) PDF

Technology for SOI Materials

Co-Chairs: P.L.F. Hemment and K. Izumi

TimeAbs#TitleView
2:00473 Variants on Bonded SOI for Advanced ICs - H. Gamble (The Queen`s University of Belfast) PDF
2:30474 Ion Beam Synthesis of SiC on Insulator Structures - S. Christophe, P.-R. Alejandro, R.-R. Albert, M. Joan Ramon (Universitat de Barcelona), E. Jaume, A. Maria Cruz (Centre Nacional de Microelectronica CNM-CSIC), P. Dieter, K. Reinhard, and S. Wolfgang (Forschungszentrum Rossendorf) PDF
2:45475 Relaxed SiGe On Insulator Fabricated via Wafer Bonding and Layer Transfer: Etch-back and Smart-cut Alternatives - G. Taraschi, Z.-Y. Cheng, M.T. Currie, C.W. Leitz, T.A. Langdo, M.L. Lee, A. Pitera, E.A. Fitzgerald, D.A. Antoniadis, and J.L. Hoyt (Massachusetts Institute of Technology) PDF
3:00 Thirty-Minute Intermission
3:30476 Recent Advances in SOS Material and Devices - Y. Moriyasu, T. Morishita, M. Matsui, and A. Yasujima (Asahi Chemical Industry Co., Ltd.) PDF
4:00477 From SOI to SOIM technology: Application for specific semiconductor processes - O. Rayssac (SOITEC S.A), H. Moriceau, M. Olivier (LETI/CEA), I. Stoimenos (Aristotle University of Thessaloniki), A.M. Cartier, and B. Aspar (LETI/CEA) PDF
4:15478 Volume Production in ELTRANr SOI-Epi WafersTM - H. Isaj, J. Nakayama, and T. Yonehara (ELTRAN Business Center) GIF
4:45479 The BELPHI-SOI Technology - G. Amato, L. Boarino, A.M. Rossi, S. Borini (Istituto Elettrotecnico Nazionale Galileo Ferraris), G. Lulli, and A. Parisini (CNR-LAMEL) PDF
5:00480 Electrolytic Hydrogenation of Buried Preamorphized Layer in Silicon for SOI Wafer Process - A. Usenko (Silicon Wafer Technologies, Inc.) and W. Carr (New Jersey Institute of Technology) PDF
5:15481 Silicon on Insulator Materials Created by Microwave Hybrid - T.H. Lee, J. Lin, and J. Peng (Taiwan Semiconductor Wafer Bonding Co.) PDF
5:30482 Atomic-Layer Cleaving for SOI Wafer Fabrication and a Path Towards Laminated Electronics - M.I. Current, I.J. Malik, S.W. Bedell, H. Kirk, M. Korolik, S. Kang, and F.J. Henley (Silicon Genesis Corporation) PDF

Tuesday, March 27, 2001

Material Characterization and Device Physics

Co-Chairs: H. Gamble and J. Fossum

TimeAbs#TitleView
8:30483 Defects and Strain in Hydrogen and Helium Co-Implanted Silicon - X. Duo, W. Liu, M. Zhang (Chinese Academy of Sciences), S.X. Wang, L.M. Wang (The University of Michigan), and C. Lin (Chinese Academy of Sciences) PDF
8:45484 Non-deatructive Impulsive Stimulated Thermal Scattering (ISTS) Analysis of SOI defects in SIMOX - M.J. Anc (Ibis Technology Corporation), M. Gostein, M. Banet (Philips Analytical), and L.P. Allen (Epion Corp.) PDF
9:00485 Detection of SOI Fatal Defects by Cu Decoration in Conjunction with HF Immersion - K. Notsu, N. Honma, and T. Yonehara (Canon Inc.) PDF
9:15486 Analysis of Microstructural Properties of SIMOX Wafers with Photoluminescence - V. Higgs (Accent Semiconductor Technologies (U.K.) Ltd.) and M.J. Anc (Ibis Technology Corporation) PDF
9:30 Thirty-Minute Intermission
10:00487 Monte Carlo Simulation of Transport in Silicon-on-Insulator Inversion Layers - F. Gamiz (Universidad de Granada) PDF
10:30488 Study of Self-Heating Effect on Device Performance of Sub-0.1um SOI MOSFETs Including Velocity Overshoot - S. Kawanaka, K. Matsuzawa, K. Inoh, Y. Katsumata, M. Yoshimi, and H. Ishiuchi (Toshiba Corporation) PDF
10:45489 Analysis of Non-Stationary Transport and Quantum Effects in Realistic 0.1um Partially-Depleted SOI Technology - D. Munteanu, G. Lecarval, and C. Fenouillet-Beranger (LETI) PDF
11:00490 Modeling Short-Channel Effects in SOI MOSFETs - D. Monroe (Bell Labs, Lucent Technologies), S.-H. Oh (Stanford University), and J.M. Hergenrother (Bell Labs, Lucent Technologies) PDF
11:30491 A Simulation Study of Partially Depleted SOI MOSFETs - M. Gritsch, H. Kosina, T. Grasser, and S. Selberherr (Technical University of Vienna) PDF
11:45492 A New Fully-Depleted SOI MOSFET Macro-Model Valid from DC to RF - B. Iniguez, J.-P. Raskin, L. Demeûs, A. Nève, M. Goffioul, P. Simon, D. Vanhoenacker, and D. Flandre (UCL) PDF

Electrical Characterization and Properties

Co-Chairs: G.K. Celler and C. Tretz

TimeAbs#TitleView
2:00493 Electrical Properties of Metal-Buried Oxide-Silicon Structures Fabricated by Low Dose SIMOX Process - P. Dimitrakis, G. Papaioannou (University of Athens), and S. Cristoloveanu (LPCS-ENSERG/INPG) PDF
2:15494 Extraction of the Oxide Charge Density at Front and Back Interfaces of SOI nMOSFETs Devices - A.S. Nicolett (CEETEPS/FATEC), J.A. Martino (Escola Politecnica da Universidade de Sao Paulo), E. Simoen, and C. Claeys (IMEC) PDF
2:30495 MOSFFET Based "Gated-Diode" Characterization of the Buried Oxide Interface of Irradiated and non-Irradiated SIMOX and UNIBOND Wafers - D. Ioannou, A. Salman (George Mason University), R.K. Lawrence, W. Jenkins (ISFA Inc.), and S.T. Liu (Honeywell) PDF
2:45496 Measurements of Low Field Mobility in Ultre-Thin SOI n- and p-Mosfets - M. Mastrapasqua, D. Esseni, G.K. Celler, F.H. Baumann (Bell Labs, Lucent Technologies), C. Fiegna, L. Selmi, and E. Sangiorgi (DIEGM - Univ. of Udine) PDF
3:00 Thirty-Minute Intermission
3:30497 Electrical Characterization of Bonded SOI with Hg-contact “Horseshoe” Probes and InGa-contact “H-FET” Structures - H. Kirk, S. Bedell, and M. Current (Silicon Genesis Corporation) PDF
3:45498 Charge Injection Characterization of Thin-Film SOI MOS Transistors at High Temperature - G. Picun, L. Demeus (CISSOID S.A.), and D. Flandre (Universite Catholique de Louvain) PDF
4:00499 Total Dose Radiation Response of 0.25 Micron SOI PD CMOS Transistors - M. Liu (Honeywell, SSEC), W. Jenkins (Naval Research Laboratory), and T. Barge (SOITEC, SA) PDF
4:15500 Cryogenic Operation of Fully-Depleted SOI nFETs - Y. Li, J.D. Cressler, G. Niu (Auburn University), and J. Patel (Jet Propulsion Laboratory) PDF
4:30501 Evaluation and Comparison of Various Silicon-On-Sapphire (SOS) Materials using the Pseudo-MOSFET Technique - N. Hefyene (Swiss Federal Institute of Technology of Lausanne (EPFL), EPFL – LEG - ELB Ecublens, CH – 1015 Lausanne, Switzerland,) and S. Cristoloveanu (Laboratoire de Physique des Composants a Semiconducteurs (UA-CNRS & INPG), ENSERG, B.P. 257, 38016 Grenoble Cedex 1, France,) PDF
4:45502 Trapping and Annealing of Charge Generated by FN Electron Injection in Buried Oxide of SIMOX and UNIBOND SOI Structures - A. Nazarov, V. Kilchyska, I. Barchuk, and A. Tkachenko (NASU) PDF
5:00503 Channel Width, Length and Thickness Effects in LOCOS Isolated SOI MOSFETs - J. Pretet, S. Cristoloveanu (LPCS), T. Ernst (STMicroelectronics), and F. Allibert (Soitec) PDF
5:15504 Observation of Bulk-Trap Induced Generation-Recombination Noise in the FD SOI MOSFET - Z. Lun, D.S. Ang, and C.H. Ling (National University of Singapore) PDF
5:30505 Determination of Silicon Film Doping Concentration and Back Oxide Charge Density using SOI-MOS Capacitor - V. Sonnenberg (FATEC/SP/CEETEPS) and J.A. Martino (Universidade de Sao Paulo) PDF

Wednesday, March 28, 2001

Devices, Circuits and Applications I

Co-Chairs: Y.W. Kim and D. Ioannou

TimeAbs#TitleView
10:00506 SOI Materials and Devices: A Designer Viewpoint - C. Tretz (Advanced Micro Devices) PDF
10:30507 Silicon-on-Sapphire Technology: QUO VADIS II A Competitive Alternative for RF Systems - I. Lagnado and P. de la Houssaye (SPAWAR Systems Center San Diego) PDF
10:45508 Improvement of sub-0.25 um Fully-Depleted SOI CMOS Analog Performance by Thinning the Si Film - A. Neve, V. Dessard, P. Delatte, V. Brodéoux, B. Iniguez, E. Rauly, and D. Flandre (Universite Catholique de Louvain) PDF
11:00509 Reduction of Dynamic Leakage Current for 0.18um SOI Devices by Using Retrograded Channel Structure - H. Kang, B. Kim, J. Jin, Y. Kim, and K. Suh (Samsung Electronics) PDF
11:15510 Improved LOCOS Isolation for Ultra Thin 0.18 um Fully-Depleted SOI CMOS - H. van Meer (IMEC) and K. De Meyer (INSYS) PDF
11:30511 Effect of SiGe Layer on Electrical Characteristics of SGI-PDSOI MOSFETs - T.-H. Choe, G.J. Bae, S.S. Kim, H.S. Rhee, K.W. Lee, N.I. Lee, H.S. Kang, K. Fujihara, H.K. Kang, and J.T. Moon (Samsung Electronics Co., Ltd) PDF
11:45512 Characterization of Thin-Film SOI Split-Drain MOS Transistors as Magnetic Sensors - G. Picun (CISSOID S.A.) and D. Flandre (Universite catholique de Louvain) PDF

Device Physics

Co-Chairs: D. Monroe and P. Ashburn

TimeAbs#TitleView
2:00513 Modeling, Simulation and Design Kit for SOI - O. Faynot, J.L. Pelloie, and M. Belleville (LETI) PDF
2:30514 Impact of Body-to-Body Leakage on MOSFET Design Scaling in Partially Depleted SOI - J. Sleight, A. Bryant, W. Clark, M. Ieong, E. Nowak, W. Rausch, and M. Sherony (IBM) PDF
2:45515 Hot-Carrier Effects in Deep Submicron SOI-MOSFETs During Off-State Operation: Aging Characteristics and Defect Evaluation - P. Dimitrakis (University of Athens), J. Jomaah, F. Balestra (LPCS-ENSERG/INPG), and G. Papaioannou (University of Athens) PDF
3:00 Thirty-Minute Intermission
3:30516 Special Frequency-Dependent Transient Mechanisms in SOI MOSFETs Measured by a New Technique: The Average Transient Current - T. Ernst (LPCS), S. Lakeou (University of the District of Columbia), F. Allibert, and S. Cristoloveanu (LPCS) PDF
3:45517 Theoretical Prediction of Switching in MOS/SOI Transistor with Ultrathin Oxide - B. Majkusiak (Warsaw University of Technology) PDF
4:00518 Silicon-on-Insulator (SOI) MOSFET Structure for Sub-50-um Channel Regime - Y. Omura (Kansai University) GIF
4:15519 Influence of the Back Gate Bias on the Properties of SOI LDMOSFETs - A. Vandooren (University of California, Davis) and S. Cristoloveanu (ENSERG) PDF
4:30520 A Compact Model for SOI LDMOST, Including Accumulation, Lateral Doping Gradient and High Side Behaviour - N. D'Halleweyn, J. Benson (University of Southampton), M. Swanenberg (Philips Semiconductors), and W. Redman-White (University of Southampton) PDF
4:45521 Suppression of the Floating Body Effect with SiGe Source Structure for Fully Depleted SOI MOSFET's - Y.G. Ko, H.S. Kang, B.S. Kim, Y.W. Kim, and K.P. Suh (Samsung Electronics Co, Ltd) PDF

Thursday, March 29, 2001

Innovating SOI Devices

Co-Chairs: M. Itoh and T. Skotniki

TimeAbs#TitleView
8:30522 Fabrication of a Self-Aligned SOI Nano Flash Memory Device - X. Tang, X. Baie (Universite Cathonique de Louvain), J.-P. Colinge (University of California, Davis), F. Van de Wiele, and V. Bayot (Universite Cathonique de Louvain) PDF
8:45523 Potential of Surface Accumulation Mode for Deep-Submicron Fully-Depleted SOI CMOS Technologies - B. Iniguez, E. Rauly, and D. Flandre (UCL) PDF
9:00524 Advanced RESURF Concepts in SOI Devices - Optimisation and Fabrication - A. Popescu, F. Udrea, K. Sheng, D. Garner, H.-T. Lim, R. Ng, G. Khoo, and W. Milne (Cambridge University) PDF
9:15525 Avalanche Currents in High-Voltage, Thin-Film Silicon-on-Insulator Devices - R.P. Zingg, H. Gerritsen, and I. Weijland-Emmerik (Philips Semiconductors Consumer Systems) PDF
9:30 Thirty-Minute Intermission
10:00526 SiGe Heterojunction Bipolar Transistors on Insulator - P. Ashburn, H. El Mubarek, J. Bonar, and B. Redman-White (University of Southampton) PDF
10:30527 New Quantum-Confinement Based SOI Single-Hole Teansistor - X. Tang (Universite Catholique de Louvain) PDF
10:45528 A Tunneling-Barrier Junction MOSFET on SOI Substrates with a Suppressed Short-Channel Effect for the Ultimate Device Structure - Y. Omura (Kansai University) GIF
11:00529 A Fully Depleted Delta-channel SOI NMOSFET - Z. Jiao and A. Salama (University of Toronto) PDF
11:15530 A Process-Based Compact Model for Double-Gate MOSFETs - M.-H. Chiang and J. Fossum (University of Florida) PDF
11:30531 Performance of Double-Gate SOI nMOSFETs (Gate-All-Around) at Low Temperature - A. Vandooren (University of california, Davis), S. Cristoloveanu (LPCS-ENSERG), J.-P. Colinge (University of california, Davis), and D. Flandre (Universite catholique de Louvain) PDF
11:45532 Nano Gap Fabrication by Thermal Stress Cleavage on SIMOX SOI for Lateral FED Application - Y.-H. Bae (Uiduk University), W.-J. Zang, S.-H. Hahm, J.-H. Lee, and J.-H. Lee (Kyungpook National University) PDF

Devices, Circuits and Applications II

Co-Chairs: F. Assaderaghi and I. Lagnado

TimeAbs#TitleView
1:30533 Mixed-Signal LSI Technology using SOI Device for Fingertip Communicator - Y. Kado, Y. Matsuya, T. Douseki, S. Nakata, T. Tsukahara, and J. Yamada (NTT Telecommunications Energy Laboratories) PDF
2:00534 Combining SOI Technology and Asynchronous Techniques for Power Reduction - D. Donaghy, S. Hall (University of Liverpool), and L. Brackenbury (University of Manchester) PDF
2:15535 High Performance Current-Mirror Using Graded-Channel SOI NMOSFETS - M. Pavanello (State University of Campinas (UNICAMP)), J. Martino (Polytechnique School of University of Sao Paulo), and D. Flandre (Universite Catholique de Louvain) PDF
2:30536 Isolation Techniques, Parasitic Sidewall Conduction and Narrow Channel Effects on SOI MOSFET's - D. Ioannou (George Mason University) PDF
3:00 Thirty-Minute Intermission
3:30537 Fully Depleted SIMOX SOI Process Technology for Low Power Digital and RF Device - M. Itoh, Y. Kawai, S. Ito, K. Yokomizo, Y. Katakura, Y. Fukuda, and F. Ichikawa (OKI Electric Industry Co., Ltd.) PDF
4:00538 Validation of Extracted High Frequency Small Signal Parameters on SOI devices - A. Bracale, V. Ferlet-Cavrois, N. Fel (CEA/DIF), J.-L. Gautier (ENSEA), J.-L. Pelloie, and J. de Poncharra (CEA/DTA/LETI) PDF
4:15539 Design Considerations for SOI Charge Pump Circuits - D. Ioannou, N. Subba, S. Mitra (George Mason University), and C. Tretz (AMD) PDF
4:30540 Modeling of the Leakage Drain Current in Accumulation-Mode SOI pMOSFETs for High-Temperature Applications - M. Bellodi (Escola Politecnica da USP, Laboratório de Sistemas Integraveis - LSI/PSI/USP), B. Iniguez, D. Flandre (Universite Catholique de Louvain), and J.A. Martino (Escola Politecnica da USP, Laboratório de Sistemas Integraveis - LSI/PSI/USP) PDF